##
## This file is part of the coreboot project.
##
## Copyright (C) 2010 Nils Jacobs
##
## This program is free software; you can redistribute it and/or
## modify it under the terms of the GNU General Public License as
## published by the Free Software Foundation; version 2 of
## the License.
##
## This program is distributed in the hope that it will be useful,
## but WITHOUT ANY WARRANTY; without even the implied warranty of
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
## GNU General Public License for more details.
##
## You should have received a copy of the GNU General Public License
## along with this program; if not, write to the Free Software
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
## MA 02110-1301 USA
##

chip northbridge/amd/gx2
	register "irqmap" = "0xaa5b"

	device lapic_cluster 0 on
		chip cpu/amd/model_gx2
			device lapic 0 on end
		end
	end
  	device pci_domain 0 on 
    		device pci 1.0 on end
		device pci 1.1 on end
      		chip southbridge/amd/cs5536
			register "enable_gpio_int_route" = "0x0D0C0700"
			register "enable_ide_nand_flash" = "0" # 0:ide mode, 1:flash
			register "enable_USBP4_device" = "0"	#0: host, 1:device
			register "enable_USBP4_overcurrent" = "0" #0:off, xxxx:overcurrent setting CS5536 Data Book (pages 380-381)
			register "com1_enable" = "1"
			register "com1_address" = "0x3F8"
			register "com1_irq" = "4"
			register "com2_enable" = "0"
			register "com2_address" = "0x2F8"
			register "com2_irq" = "3"
        		device pci e.0 on end	# Realtek 8139 LAN
        		device pci f.0 on end	# ISA Bridge
        		device pci f.2 on end	# IDE Controller
        		device pci f.3 on end 	# Audio
        		device pci f.4 on end	# OHCI
			device pci f.5 on end	# EHCI
      		end
    	end
end

