#include <device/device.h>
#include <device/pci.h>
#include "cpu/amd/agesa_wrapper/family14/chip.h"
#include "mainboard/amd/persimmon/chip.h"
#include "northbridge/amd/agesa_wrapper/family14/chip.h"
#include "northbridge/amd/agesa_wrapper/family14/root_complex/chip.h"
#include "southbridge/amd/cimx_wrapper/sb800/chip.h"
#include "superio/fintek/f81865f/chip.h"

/* pass 0 */
struct bus dev_root_links[];
static struct device _dev2;
struct bus _dev2_links[];
static struct device _dev5;
struct bus _dev5_links[];
static struct device _dev4;
static struct device _dev47;
static struct device _dev48;
static struct device _dev49;
static struct device _dev50;
static struct device _dev51;
static struct device _dev52;
static struct device _dev53;
static struct device _dev54;
static struct device _dev8;
static struct device _dev9;
static struct device _dev10;
static struct device _dev11;
static struct device _dev12;
static struct device _dev13;
static struct device _dev14;
static struct device _dev15;
static struct device _dev17;
static struct device _dev18;
static struct device _dev19;
static struct device _dev20;
static struct device _dev21;
static struct device _dev22;
static struct device _dev23;
static struct device _dev24;
struct bus _dev24_links[];
static struct device _dev29;
static struct device _dev30;
static struct device _dev31;
struct bus _dev31_links[];
static struct device _dev41;
static struct device _dev42;
static struct device _dev43;
static struct device _dev44;
static struct device _dev45;
static struct device _dev46;
static struct device _dev26;
static struct device _dev28;
static struct device _dev33;
struct resource _dev33_res[];
static struct device _dev34;
static struct device _dev35;
static struct device _dev36;
struct resource _dev36_res[];
static struct device _dev37;
static struct device _dev38;
static struct device _dev39;
struct resource _dev39_res[];
static struct device _dev40;
struct resource _dev40_res[];

/* pass 1 */
struct mainboard_config mainboard_info_0;
struct device *last_dev = &_dev54;
struct device dev_root = {
	.ops = &default_dev_ops_root,
	.bus = &dev_root_links[0],
	.path = { .type = DEVICE_PATH_ROOT },
	.enabled = 1,
	.on_mainboard = 1,
	.link_list = &dev_root_links[0],
	.chip_ops = &mainboard_ops,
	.chip_info = &mainboard_info_0,
	.next=&_dev2
};
struct bus dev_root_links[] = {
		[0] = {
			.link_num = 0,
			.dev = &dev_root,
			.children = &_dev2,
			.next = NULL,
		},
	};
struct northbridge_amd_agesa_wrapper_family14_root_complex_config northbridge_amd_agesa_wrapper_family14_root_complex_info_1;
static struct device _dev2 = {
	.ops = 0,
	.bus = &dev_root_links[0],
	.path = {.type=DEVICE_PATH_APIC_CLUSTER,{.apic_cluster={ .cluster = 0x0 }}},
	.enabled = 1,
	.on_mainboard = 1,
	.link_list = &_dev2_links[0],
	.sibling = &_dev5,
	.chip_ops = &northbridge_amd_agesa_wrapper_family14_root_complex_ops,
	.chip_info = &northbridge_amd_agesa_wrapper_family14_root_complex_info_1,
	.next=&_dev4
};
struct bus _dev2_links[] = {
		[0] = {
			.link_num = 0,
			.dev = &_dev2,
			.children = &_dev4,
			.next = NULL,
		},
	};
static struct device _dev5 = {
	.ops = 0,
	.bus = &dev_root_links[0],
	.path = {.type=DEVICE_PATH_PCI_DOMAIN,{.pci_domain={ .domain = 0x0 }}},
	.enabled = 1,
	.on_mainboard = 1,
	.subsystem_vendor = 0x1022,
	.subsystem_device = 0x1510,
	.link_list = &_dev5_links[0],
	.chip_ops = &northbridge_amd_agesa_wrapper_family14_root_complex_ops,
	.chip_info = &northbridge_amd_agesa_wrapper_family14_root_complex_info_1,
	.next=&_dev8
};
struct bus _dev5_links[] = {
		[0] = {
			.link_num = 0,
			.dev = &_dev5,
			.children = &_dev8,
			.next = NULL,
		},
	};
struct cpu_amd_agesa_wrapper_family14_config cpu_amd_agesa_wrapper_family14_info_3;
static struct device _dev4 = {
	.ops = 0,
	.bus = &_dev2_links[0],
	.path = {.type=DEVICE_PATH_APIC,{.apic={ .apic_id = 0x0 }}},
	.enabled = 1,
	.on_mainboard = 1,
	.link_list = NULL,
	.chip_ops = &cpu_amd_agesa_wrapper_family14_ops,
	.chip_info = &cpu_amd_agesa_wrapper_family14_info_3,
	.next=&_dev5
};
struct northbridge_amd_agesa_wrapper_family14_config northbridge_amd_agesa_wrapper_family14_info_6;
struct northbridge_amd_agesa_wrapper_family14_config northbridge_amd_agesa_wrapper_family14_info_7;
struct southbridge_amd_cimx_wrapper_sb800_config southbridge_amd_cimx_wrapper_sb800_info_16	= {
	.boot_switch_sata_ide = 0,
	.gpp_configuration = 0,
};

static struct device _dev47 = {
	.ops = 0,
	.bus = &_dev5_links[0],
	.path = {.type=DEVICE_PATH_PCI,{.pci={ .devfn = PCI_DEVFN(0x18,0)}}},
	.enabled = 1,
	.on_mainboard = 1,
	.subsystem_vendor = 0x1022,
	.subsystem_device = 0x1510,
	.link_list = NULL,
	.sibling = &_dev48,
	.chip_ops = &northbridge_amd_agesa_wrapper_family14_ops,
	.chip_info = &northbridge_amd_agesa_wrapper_family14_info_6,
	.next=&_dev48
};
static struct device _dev48 = {
	.ops = 0,
	.bus = &_dev5_links[0],
	.path = {.type=DEVICE_PATH_PCI,{.pci={ .devfn = PCI_DEVFN(0x18,1)}}},
	.enabled = 1,
	.on_mainboard = 1,
	.subsystem_vendor = 0x1022,
	.subsystem_device = 0x1510,
	.link_list = NULL,
	.sibling = &_dev49,
	.chip_ops = &northbridge_amd_agesa_wrapper_family14_ops,
	.chip_info = &northbridge_amd_agesa_wrapper_family14_info_6,
	.next=&_dev49
};
static struct device _dev49 = {
	.ops = 0,
	.bus = &_dev5_links[0],
	.path = {.type=DEVICE_PATH_PCI,{.pci={ .devfn = PCI_DEVFN(0x18,2)}}},
	.enabled = 1,
	.on_mainboard = 1,
	.subsystem_vendor = 0x1022,
	.subsystem_device = 0x1510,
	.link_list = NULL,
	.sibling = &_dev50,
	.chip_ops = &northbridge_amd_agesa_wrapper_family14_ops,
	.chip_info = &northbridge_amd_agesa_wrapper_family14_info_6,
	.next=&_dev50
};
static struct device _dev50 = {
	.ops = 0,
	.bus = &_dev5_links[0],
	.path = {.type=DEVICE_PATH_PCI,{.pci={ .devfn = PCI_DEVFN(0x18,3)}}},
	.enabled = 1,
	.on_mainboard = 1,
	.subsystem_vendor = 0x1022,
	.subsystem_device = 0x1510,
	.link_list = NULL,
	.sibling = &_dev51,
	.chip_ops = &northbridge_amd_agesa_wrapper_family14_ops,
	.chip_info = &northbridge_amd_agesa_wrapper_family14_info_6,
	.next=&_dev51
};
static struct device _dev51 = {
	.ops = 0,
	.bus = &_dev5_links[0],
	.path = {.type=DEVICE_PATH_PCI,{.pci={ .devfn = PCI_DEVFN(0x18,4)}}},
	.enabled = 1,
	.on_mainboard = 1,
	.subsystem_vendor = 0x1022,
	.subsystem_device = 0x1510,
	.link_list = NULL,
	.sibling = &_dev52,
	.chip_ops = &northbridge_amd_agesa_wrapper_family14_ops,
	.chip_info = &northbridge_amd_agesa_wrapper_family14_info_6,
	.next=&_dev52
};
static struct device _dev52 = {
	.ops = 0,
	.bus = &_dev5_links[0],
	.path = {.type=DEVICE_PATH_PCI,{.pci={ .devfn = PCI_DEVFN(0x18,5)}}},
	.enabled = 1,
	.on_mainboard = 1,
	.subsystem_vendor = 0x1022,
	.subsystem_device = 0x1510,
	.link_list = NULL,
	.sibling = &_dev53,
	.chip_ops = &northbridge_amd_agesa_wrapper_family14_ops,
	.chip_info = &northbridge_amd_agesa_wrapper_family14_info_6,
	.next=&_dev53
};
static struct device _dev53 = {
	.ops = 0,
	.bus = &_dev5_links[0],
	.path = {.type=DEVICE_PATH_PCI,{.pci={ .devfn = PCI_DEVFN(0x18,6)}}},
	.enabled = 1,
	.on_mainboard = 1,
	.subsystem_vendor = 0x1022,
	.subsystem_device = 0x1510,
	.link_list = NULL,
	.sibling = &_dev54,
	.chip_ops = &northbridge_amd_agesa_wrapper_family14_ops,
	.chip_info = &northbridge_amd_agesa_wrapper_family14_info_6,
	.next=&_dev54
};
static struct device _dev54 = {
	.ops = 0,
	.bus = &_dev5_links[0],
	.path = {.type=DEVICE_PATH_PCI,{.pci={ .devfn = PCI_DEVFN(0x18,7)}}},
	.enabled = 1,
	.on_mainboard = 1,
	.subsystem_vendor = 0x1022,
	.subsystem_device = 0x1510,
	.link_list = NULL,
	.chip_ops = &northbridge_amd_agesa_wrapper_family14_ops,
	.chip_info = &northbridge_amd_agesa_wrapper_family14_info_6,
};
static struct device _dev8 = {
	.ops = 0,
	.bus = &_dev5_links[0],
	.path = {.type=DEVICE_PATH_PCI,{.pci={ .devfn = PCI_DEVFN(0x0,0)}}},
	.enabled = 1,
	.on_mainboard = 1,
	.subsystem_vendor = 0x1022,
	.subsystem_device = 0x1510,
	.link_list = NULL,
	.sibling = &_dev9,
	.chip_ops = &northbridge_amd_agesa_wrapper_family14_ops,
	.chip_info = &northbridge_amd_agesa_wrapper_family14_info_7,
	.next=&_dev9
};
static struct device _dev9 = {
	.ops = 0,
	.bus = &_dev5_links[0],
	.path = {.type=DEVICE_PATH_PCI,{.pci={ .devfn = PCI_DEVFN(0x1,0)}}},
	.enabled = 1,
	.on_mainboard = 1,
	.subsystem_vendor = 0x1022,
	.subsystem_device = 0x1510,
	.link_list = NULL,
	.sibling = &_dev10,
	.chip_ops = &northbridge_amd_agesa_wrapper_family14_ops,
	.chip_info = &northbridge_amd_agesa_wrapper_family14_info_7,
	.next=&_dev10
};
static struct device _dev10 = {
	.ops = 0,
	.bus = &_dev5_links[0],
	.path = {.type=DEVICE_PATH_PCI,{.pci={ .devfn = PCI_DEVFN(0x1,1)}}},
	.enabled = 1,
	.on_mainboard = 1,
	.subsystem_vendor = 0x1022,
	.subsystem_device = 0x1510,
	.link_list = NULL,
	.sibling = &_dev11,
	.chip_ops = &northbridge_amd_agesa_wrapper_family14_ops,
	.chip_info = &northbridge_amd_agesa_wrapper_family14_info_7,
	.next=&_dev11
};
static struct device _dev11 = {
	.ops = 0,
	.bus = &_dev5_links[0],
	.path = {.type=DEVICE_PATH_PCI,{.pci={ .devfn = PCI_DEVFN(0x4,0)}}},
	.enabled = 1,
	.on_mainboard = 1,
	.subsystem_vendor = 0x1022,
	.subsystem_device = 0x1510,
	.link_list = NULL,
	.sibling = &_dev12,
	.chip_ops = &northbridge_amd_agesa_wrapper_family14_ops,
	.chip_info = &northbridge_amd_agesa_wrapper_family14_info_7,
	.next=&_dev12
};
static struct device _dev12 = {
	.ops = 0,
	.bus = &_dev5_links[0],
	.path = {.type=DEVICE_PATH_PCI,{.pci={ .devfn = PCI_DEVFN(0x5,0)}}},
	.enabled = 0,
	.on_mainboard = 1,
	.subsystem_vendor = 0x1022,
	.subsystem_device = 0x1510,
	.link_list = NULL,
	.sibling = &_dev13,
	.chip_ops = &northbridge_amd_agesa_wrapper_family14_ops,
	.chip_info = &northbridge_amd_agesa_wrapper_family14_info_7,
	.next=&_dev13
};
static struct device _dev13 = {
	.ops = 0,
	.bus = &_dev5_links[0],
	.path = {.type=DEVICE_PATH_PCI,{.pci={ .devfn = PCI_DEVFN(0x6,0)}}},
	.enabled = 0,
	.on_mainboard = 1,
	.subsystem_vendor = 0x1022,
	.subsystem_device = 0x1510,
	.link_list = NULL,
	.sibling = &_dev14,
	.chip_ops = &northbridge_amd_agesa_wrapper_family14_ops,
	.chip_info = &northbridge_amd_agesa_wrapper_family14_info_7,
	.next=&_dev14
};
static struct device _dev14 = {
	.ops = 0,
	.bus = &_dev5_links[0],
	.path = {.type=DEVICE_PATH_PCI,{.pci={ .devfn = PCI_DEVFN(0x7,0)}}},
	.enabled = 0,
	.on_mainboard = 1,
	.subsystem_vendor = 0x1022,
	.subsystem_device = 0x1510,
	.link_list = NULL,
	.sibling = &_dev15,
	.chip_ops = &northbridge_amd_agesa_wrapper_family14_ops,
	.chip_info = &northbridge_amd_agesa_wrapper_family14_info_7,
	.next=&_dev15
};
static struct device _dev15 = {
	.ops = 0,
	.bus = &_dev5_links[0],
	.path = {.type=DEVICE_PATH_PCI,{.pci={ .devfn = PCI_DEVFN(0x8,0)}}},
	.enabled = 0,
	.on_mainboard = 1,
	.subsystem_vendor = 0x1022,
	.subsystem_device = 0x1510,
	.link_list = NULL,
	.sibling = &_dev17,
	.chip_ops = &northbridge_amd_agesa_wrapper_family14_ops,
	.chip_info = &northbridge_amd_agesa_wrapper_family14_info_7,
	.next=&_dev17
};
static struct device _dev17 = {
	.ops = 0,
	.bus = &_dev5_links[0],
	.path = {.type=DEVICE_PATH_PCI,{.pci={ .devfn = PCI_DEVFN(0x11,0)}}},
	.enabled = 1,
	.on_mainboard = 1,
	.subsystem_vendor = 0x1022,
	.subsystem_device = 0x1510,
	.link_list = NULL,
	.sibling = &_dev18,
	.chip_ops = &southbridge_amd_cimx_wrapper_sb800_ops,
	.chip_info = &southbridge_amd_cimx_wrapper_sb800_info_16,
	.next=&_dev18
};
static struct device _dev18 = {
	.ops = 0,
	.bus = &_dev5_links[0],
	.path = {.type=DEVICE_PATH_PCI,{.pci={ .devfn = PCI_DEVFN(0x12,0)}}},
	.enabled = 1,
	.on_mainboard = 1,
	.subsystem_vendor = 0x1022,
	.subsystem_device = 0x1510,
	.link_list = NULL,
	.sibling = &_dev19,
	.chip_ops = &southbridge_amd_cimx_wrapper_sb800_ops,
	.chip_info = &southbridge_amd_cimx_wrapper_sb800_info_16,
	.next=&_dev19
};
static struct device _dev19 = {
	.ops = 0,
	.bus = &_dev5_links[0],
	.path = {.type=DEVICE_PATH_PCI,{.pci={ .devfn = PCI_DEVFN(0x12,1)}}},
	.enabled = 1,
	.on_mainboard = 1,
	.subsystem_vendor = 0x1022,
	.subsystem_device = 0x1510,
	.link_list = NULL,
	.sibling = &_dev20,
	.chip_ops = &southbridge_amd_cimx_wrapper_sb800_ops,
	.chip_info = &southbridge_amd_cimx_wrapper_sb800_info_16,
	.next=&_dev20
};
static struct device _dev20 = {
	.ops = 0,
	.bus = &_dev5_links[0],
	.path = {.type=DEVICE_PATH_PCI,{.pci={ .devfn = PCI_DEVFN(0x12,2)}}},
	.enabled = 1,
	.on_mainboard = 1,
	.subsystem_vendor = 0x1022,
	.subsystem_device = 0x1510,
	.link_list = NULL,
	.sibling = &_dev21,
	.chip_ops = &southbridge_amd_cimx_wrapper_sb800_ops,
	.chip_info = &southbridge_amd_cimx_wrapper_sb800_info_16,
	.next=&_dev21
};
static struct device _dev21 = {
	.ops = 0,
	.bus = &_dev5_links[0],
	.path = {.type=DEVICE_PATH_PCI,{.pci={ .devfn = PCI_DEVFN(0x13,0)}}},
	.enabled = 1,
	.on_mainboard = 1,
	.subsystem_vendor = 0x1022,
	.subsystem_device = 0x1510,
	.link_list = NULL,
	.sibling = &_dev22,
	.chip_ops = &southbridge_amd_cimx_wrapper_sb800_ops,
	.chip_info = &southbridge_amd_cimx_wrapper_sb800_info_16,
	.next=&_dev22
};
static struct device _dev22 = {
	.ops = 0,
	.bus = &_dev5_links[0],
	.path = {.type=DEVICE_PATH_PCI,{.pci={ .devfn = PCI_DEVFN(0x13,1)}}},
	.enabled = 1,
	.on_mainboard = 1,
	.subsystem_vendor = 0x1022,
	.subsystem_device = 0x1510,
	.link_list = NULL,
	.sibling = &_dev23,
	.chip_ops = &southbridge_amd_cimx_wrapper_sb800_ops,
	.chip_info = &southbridge_amd_cimx_wrapper_sb800_info_16,
	.next=&_dev23
};
static struct device _dev23 = {
	.ops = 0,
	.bus = &_dev5_links[0],
	.path = {.type=DEVICE_PATH_PCI,{.pci={ .devfn = PCI_DEVFN(0x13,2)}}},
	.enabled = 1,
	.on_mainboard = 1,
	.subsystem_vendor = 0x1022,
	.subsystem_device = 0x1510,
	.link_list = NULL,
	.sibling = &_dev24,
	.chip_ops = &southbridge_amd_cimx_wrapper_sb800_ops,
	.chip_info = &southbridge_amd_cimx_wrapper_sb800_info_16,
	.next=&_dev24
};
static struct device _dev24 = {
	.ops = 0,
	.bus = &_dev5_links[0],
	.path = {.type=DEVICE_PATH_PCI,{.pci={ .devfn = PCI_DEVFN(0x14,0)}}},
	.enabled = 1,
	.on_mainboard = 1,
	.subsystem_vendor = 0x1022,
	.subsystem_device = 0x1510,
	.link_list = &_dev24_links[0],
	.sibling = &_dev29,
	.chip_ops = &southbridge_amd_cimx_wrapper_sb800_ops,
	.chip_info = &southbridge_amd_cimx_wrapper_sb800_info_16,
	.next=&_dev26
};
struct bus _dev24_links[] = {
		[0] = {
			.link_num = 0,
			.dev = &_dev24,
			.children = &_dev26,
			.next = NULL,
		},
	};
static struct device _dev29 = {
	.ops = 0,
	.bus = &_dev5_links[0],
	.path = {.type=DEVICE_PATH_PCI,{.pci={ .devfn = PCI_DEVFN(0x14,1)}}},
	.enabled = 1,
	.on_mainboard = 1,
	.subsystem_vendor = 0x1022,
	.subsystem_device = 0x1510,
	.link_list = NULL,
	.sibling = &_dev30,
	.chip_ops = &southbridge_amd_cimx_wrapper_sb800_ops,
	.chip_info = &southbridge_amd_cimx_wrapper_sb800_info_16,
	.next=&_dev30
};
static struct device _dev30 = {
	.ops = 0,
	.bus = &_dev5_links[0],
	.path = {.type=DEVICE_PATH_PCI,{.pci={ .devfn = PCI_DEVFN(0x14,2)}}},
	.enabled = 1,
	.on_mainboard = 1,
	.subsystem_vendor = 0x1022,
	.subsystem_device = 0x1510,
	.link_list = NULL,
	.sibling = &_dev31,
	.chip_ops = &southbridge_amd_cimx_wrapper_sb800_ops,
	.chip_info = &southbridge_amd_cimx_wrapper_sb800_info_16,
	.next=&_dev31
};
static struct device _dev31 = {
	.ops = 0,
	.bus = &_dev5_links[0],
	.path = {.type=DEVICE_PATH_PCI,{.pci={ .devfn = PCI_DEVFN(0x14,3)}}},
	.enabled = 1,
	.on_mainboard = 1,
	.subsystem_vendor = 0x1022,
	.subsystem_device = 0x1510,
	.link_list = &_dev31_links[0],
	.sibling = &_dev41,
	.chip_ops = &southbridge_amd_cimx_wrapper_sb800_ops,
	.chip_info = &southbridge_amd_cimx_wrapper_sb800_info_16,
	.next=&_dev33
};
struct bus _dev31_links[] = {
		[0] = {
			.link_num = 0,
			.dev = &_dev31,
			.children = &_dev33,
			.next = NULL,
		},
	};
static struct device _dev41 = {
	.ops = 0,
	.bus = &_dev5_links[0],
	.path = {.type=DEVICE_PATH_PCI,{.pci={ .devfn = PCI_DEVFN(0x14,4)}}},
	.enabled = 1,
	.on_mainboard = 1,
	.subsystem_vendor = 0x1022,
	.subsystem_device = 0x1510,
	.link_list = NULL,
	.sibling = &_dev42,
	.chip_ops = &southbridge_amd_cimx_wrapper_sb800_ops,
	.chip_info = &southbridge_amd_cimx_wrapper_sb800_info_16,
	.next=&_dev42
};
static struct device _dev42 = {
	.ops = 0,
	.bus = &_dev5_links[0],
	.path = {.type=DEVICE_PATH_PCI,{.pci={ .devfn = PCI_DEVFN(0x14,5)}}},
	.enabled = 1,
	.on_mainboard = 1,
	.subsystem_vendor = 0x1022,
	.subsystem_device = 0x1510,
	.link_list = NULL,
	.sibling = &_dev43,
	.chip_ops = &southbridge_amd_cimx_wrapper_sb800_ops,
	.chip_info = &southbridge_amd_cimx_wrapper_sb800_info_16,
	.next=&_dev43
};
static struct device _dev43 = {
	.ops = 0,
	.bus = &_dev5_links[0],
	.path = {.type=DEVICE_PATH_PCI,{.pci={ .devfn = PCI_DEVFN(0x15,0)}}},
	.enabled = 0,
	.on_mainboard = 1,
	.subsystem_vendor = 0x1022,
	.subsystem_device = 0x1510,
	.link_list = NULL,
	.sibling = &_dev44,
	.chip_ops = &southbridge_amd_cimx_wrapper_sb800_ops,
	.chip_info = &southbridge_amd_cimx_wrapper_sb800_info_16,
	.next=&_dev44
};
static struct device _dev44 = {
	.ops = 0,
	.bus = &_dev5_links[0],
	.path = {.type=DEVICE_PATH_PCI,{.pci={ .devfn = PCI_DEVFN(0x15,1)}}},
	.enabled = 0,
	.on_mainboard = 1,
	.subsystem_vendor = 0x1022,
	.subsystem_device = 0x1510,
	.link_list = NULL,
	.sibling = &_dev45,
	.chip_ops = &southbridge_amd_cimx_wrapper_sb800_ops,
	.chip_info = &southbridge_amd_cimx_wrapper_sb800_info_16,
	.next=&_dev45
};
static struct device _dev45 = {
	.ops = 0,
	.bus = &_dev5_links[0],
	.path = {.type=DEVICE_PATH_PCI,{.pci={ .devfn = PCI_DEVFN(0x15,2)}}},
	.enabled = 0,
	.on_mainboard = 1,
	.subsystem_vendor = 0x1022,
	.subsystem_device = 0x1510,
	.link_list = NULL,
	.sibling = &_dev46,
	.chip_ops = &southbridge_amd_cimx_wrapper_sb800_ops,
	.chip_info = &southbridge_amd_cimx_wrapper_sb800_info_16,
	.next=&_dev46
};
static struct device _dev46 = {
	.ops = 0,
	.bus = &_dev5_links[0],
	.path = {.type=DEVICE_PATH_PCI,{.pci={ .devfn = PCI_DEVFN(0x15,3)}}},
	.enabled = 0,
	.on_mainboard = 1,
	.subsystem_vendor = 0x1022,
	.subsystem_device = 0x1510,
	.link_list = NULL,
	.sibling = &_dev47,
	.chip_ops = &southbridge_amd_cimx_wrapper_sb800_ops,
	.chip_info = &southbridge_amd_cimx_wrapper_sb800_info_16,
	.next=&_dev47
};
static struct device _dev26 = {
	.ops = 0,
	.bus = &_dev24_links[0],
	.path = {.type=DEVICE_PATH_I2C,{.i2c={ .device = 0x50 }}},
	.enabled = 1,
	.on_mainboard = 1,
	.subsystem_vendor = 0x1022,
	.subsystem_device = 0x1510,
	.link_list = NULL,
	.sibling = &_dev28,
	.next=&_dev28
};
static struct device _dev28 = {
	.ops = 0,
	.bus = &_dev24_links[0],
	.path = {.type=DEVICE_PATH_I2C,{.i2c={ .device = 0x51 }}},
	.enabled = 1,
	.on_mainboard = 1,
	.subsystem_vendor = 0x1022,
	.subsystem_device = 0x1510,
	.link_list = NULL,
	.next=&_dev29
};
struct superio_fintek_f81865f_config superio_fintek_f81865f_info_32;
static struct device _dev33 = {
	.ops = 0,
	.bus = &_dev31_links[0],
	.path = {.type=DEVICE_PATH_PNP,{.pnp={ .port = 0x4e, .device = 0x0 }}},
	.enabled = 0,
	.on_mainboard = 1,
	.subsystem_vendor = 0x1022,
	.subsystem_device = 0x1510,
	.resource_list = &_dev33_res[0],
	.link_list = NULL,
	.sibling = &_dev34,
	.chip_ops = &superio_fintek_f81865f_ops,
	.chip_info = &superio_fintek_f81865f_info_32,
	.next=&_dev34
};
struct resource _dev33_res[] = {
		{ .flags=IORESOURCE_FIXED | IORESOURCE_ASSIGNED | IORESOURCE_IO, .index=0x60, .base=0x3f0,.next=&_dev33_res[1]},
		{ .flags=IORESOURCE_FIXED | IORESOURCE_ASSIGNED | IORESOURCE_IRQ, .index=0x70, .base=0x6,.next=&_dev33_res[2]},
		{ .flags=IORESOURCE_FIXED | IORESOURCE_ASSIGNED | IORESOURCE_DRQ, .index=0x74, .base=0x2,.next=NULL },
	 };
static struct device _dev34 = {
	.ops = 0,
	.bus = &_dev31_links[0],
	.path = {.type=DEVICE_PATH_PNP,{.pnp={ .port = 0x4e, .device = 0x3 }}},
	.enabled = 0,
	.on_mainboard = 1,
	.subsystem_vendor = 0x1022,
	.subsystem_device = 0x1510,
	.link_list = NULL,
	.sibling = &_dev35,
	.chip_ops = &superio_fintek_f81865f_ops,
	.chip_info = &superio_fintek_f81865f_info_32,
	.next=&_dev35
};
static struct device _dev35 = {
	.ops = 0,
	.bus = &_dev31_links[0],
	.path = {.type=DEVICE_PATH_PNP,{.pnp={ .port = 0x4e, .device = 0x4 }}},
	.enabled = 0,
	.on_mainboard = 1,
	.subsystem_vendor = 0x1022,
	.subsystem_device = 0x1510,
	.link_list = NULL,
	.sibling = &_dev36,
	.chip_ops = &superio_fintek_f81865f_ops,
	.chip_info = &superio_fintek_f81865f_info_32,
	.next=&_dev36
};
static struct device _dev36 = {
	.ops = 0,
	.bus = &_dev31_links[0],
	.path = {.type=DEVICE_PATH_PNP,{.pnp={ .port = 0x4e, .device = 0x5 }}},
	.enabled = 1,
	.on_mainboard = 1,
	.subsystem_vendor = 0x1022,
	.subsystem_device = 0x1510,
	.resource_list = &_dev36_res[0],
	.link_list = NULL,
	.sibling = &_dev37,
	.chip_ops = &superio_fintek_f81865f_ops,
	.chip_info = &superio_fintek_f81865f_info_32,
	.next=&_dev37
};
struct resource _dev36_res[] = {
		{ .flags=IORESOURCE_FIXED | IORESOURCE_ASSIGNED | IORESOURCE_IO, .index=0x60, .base=0x60,.next=&_dev36_res[1]},
		{ .flags=IORESOURCE_FIXED | IORESOURCE_ASSIGNED | IORESOURCE_IO, .index=0x62, .base=0x64,.next=&_dev36_res[2]},
		{ .flags=IORESOURCE_FIXED | IORESOURCE_ASSIGNED | IORESOURCE_IRQ, .index=0x70, .base=0x1,.next=NULL },
	 };
static struct device _dev37 = {
	.ops = 0,
	.bus = &_dev31_links[0],
	.path = {.type=DEVICE_PATH_PNP,{.pnp={ .port = 0x4e, .device = 0x6 }}},
	.enabled = 0,
	.on_mainboard = 1,
	.subsystem_vendor = 0x1022,
	.subsystem_device = 0x1510,
	.link_list = NULL,
	.sibling = &_dev38,
	.chip_ops = &superio_fintek_f81865f_ops,
	.chip_info = &superio_fintek_f81865f_info_32,
	.next=&_dev38
};
static struct device _dev38 = {
	.ops = 0,
	.bus = &_dev31_links[0],
	.path = {.type=DEVICE_PATH_PNP,{.pnp={ .port = 0x4e, .device = 0xa }}},
	.enabled = 0,
	.on_mainboard = 1,
	.subsystem_vendor = 0x1022,
	.subsystem_device = 0x1510,
	.link_list = NULL,
	.sibling = &_dev39,
	.chip_ops = &superio_fintek_f81865f_ops,
	.chip_info = &superio_fintek_f81865f_info_32,
	.next=&_dev39
};
static struct device _dev39 = {
	.ops = 0,
	.bus = &_dev31_links[0],
	.path = {.type=DEVICE_PATH_PNP,{.pnp={ .port = 0x4e, .device = 0x10 }}},
	.enabled = 1,
	.on_mainboard = 1,
	.subsystem_vendor = 0x1022,
	.subsystem_device = 0x1510,
	.resource_list = &_dev39_res[0],
	.link_list = NULL,
	.sibling = &_dev40,
	.chip_ops = &superio_fintek_f81865f_ops,
	.chip_info = &superio_fintek_f81865f_info_32,
	.next=&_dev40
};
struct resource _dev39_res[] = {
		{ .flags=IORESOURCE_FIXED | IORESOURCE_ASSIGNED | IORESOURCE_IO, .index=0x60, .base=0x3f8,.next=&_dev39_res[1]},
		{ .flags=IORESOURCE_FIXED | IORESOURCE_ASSIGNED | IORESOURCE_IRQ, .index=0x70, .base=0x4,.next=NULL },
	 };
static struct device _dev40 = {
	.ops = 0,
	.bus = &_dev31_links[0],
	.path = {.type=DEVICE_PATH_PNP,{.pnp={ .port = 0x4e, .device = 0x11 }}},
	.enabled = 0,
	.on_mainboard = 1,
	.subsystem_vendor = 0x1022,
	.subsystem_device = 0x1510,
	.resource_list = &_dev40_res[0],
	.link_list = NULL,
	.chip_ops = &superio_fintek_f81865f_ops,
	.chip_info = &superio_fintek_f81865f_info_32,
	.next=&_dev41
};
struct resource _dev40_res[] = {
		{ .flags=IORESOURCE_FIXED | IORESOURCE_ASSIGNED | IORESOURCE_IO, .index=0x60, .base=0x2f8,.next=&_dev40_res[1]},
		{ .flags=IORESOURCE_FIXED | IORESOURCE_ASSIGNED | IORESOURCE_IRQ, .index=0x70, .base=0x3,.next=NULL },
	 };
