# 1 "build/romstage/crt0.S"
# 1 "<built-in>"
# 1 "<command-line>"
# 1 "./build/config.h" 1
# 1 "<command-line>" 2
# 1 "build/romstage/crt0.S"
# 1 "build/config.h" 1
# 2 "build/romstage/crt0.S" 2
# 1 "./src/arch/x86/init/prologue.inc" 1
# 20 "./src/arch/x86/init/prologue.inc"
# 1 "src/include/cpu/x86/post_code.h" 1

# 1 "src/include/console/post_codes.h" 1
# 3 "src/include/cpu/x86/post_code.h" 2
# 21 "./src/arch/x86/init/prologue.inc" 2
# 1 "src/include/cpu/x86/stack.h" 1
# 22 "./src/arch/x86/init/prologue.inc" 2

.section ".rom.data", "a", @progbits
.section ".rom.text", "ax", @progbits



 movb $0x01, %al; outb %al, $0x80
# 3 "build/romstage/crt0.S" 2
# 1 "./src/cpu/x86/32bit/entry32.inc" 1


# 1 "src/arch/x86/include/arch/rom_segs.h" 1
# 4 "./src/cpu/x86/32bit/entry32.inc" 2
# 1 "src/include/cpu/x86/post_code.h" 1
# 5 "./src/cpu/x86/32bit/entry32.inc" 2

 .code32







 .align 4
.globl gdtptr
gdt:
gdtptr:
 .word gdt_end - gdt -1
 .long gdt
 .word 0


 .word 0xffff, 0x0000
 .byte 0x00, 0x9b, 0xcf, 0x00


 .word 0xffff, 0x0000
 .byte 0x00, 0x93, 0xcf, 0x00

gdt_end:
# 44 "./src/cpu/x86/32bit/entry32.inc"
 .align 4
.globl protected_start
protected_start:

 lgdt %cs:gdtptr
 ljmp $0x08, $__protected_start

__protected_start:

 movl %eax, %ebp

 movb $0x10, %al; outb %al, $0x80

 movw $0x10, %ax
 movw %ax, %ds
 movw %ax, %es
 movw %ax, %ss
 movw %ax, %fs
 movw %ax, %gs


 movl %ebp, %eax
# 4 "build/romstage/crt0.S" 2
# 1 "./src/cpu/x86/fpu_enable.inc" 1
# 20 "./src/cpu/x86/fpu_enable.inc"
__fpu_start:

 movl %eax, %ebp
# 34 "./src/cpu/x86/fpu_enable.inc"
 movl %cr0, %eax
 andl $~(1 << 2), %eax
 movl %eax, %cr0


 movl %ebp, %eax
# 5 "build/romstage/crt0.S" 2
# 1 "./src/cpu/amd/agesa_wrapper/family14/cache_as_ram.inc" 1
# 30 "./src/cpu/amd/agesa_wrapper/family14/cache_as_ram.inc"
# 1 "src/vendorcode/amd/agesa/gcccar.inc" 1
# 38 "src/vendorcode/amd/agesa/gcccar.inc"
.altmacro

BSP_STACK_BASE_ADDR = 0x30000
BSP_STACK_SIZE = 0x10000
CORE0_STACK_BASE_ADDR = 0x80000
CORE0_STACK_SIZE = 0x4000
CORE1_STACK_BASE_ADDR = 0x40000
CORE1_STACK_SIZE = 0x1000

APIC_BASE_ADDRESS = 0x0000001B
  APIC_BSC = 8

AMD_MTRR_VARIABLE_BASE0 = 0x0200
AMD_MTRR_VARIABLE_BASE6 = 0x020C
AMD_MTRR_FIX64k_00000 = 0x0250
AMD_MTRR_FIX16k_80000 = 0x0258
AMD_MTRR_FIX16k_A0000 = 0x0259
AMD_MTRR_FIX4k_C0000 = 0x0268
AMD_MTRR_FIX4k_C8000 = 0x0269
AMD_MTRR_FIX4k_D0000 = 0x026A
AMD_MTRR_FIX4k_D8000 = 0x026B
AMD_MTRR_FIX4k_E0000 = 0x026C
AMD_MTRR_FIX4k_E8000 = 0x026D
AMD_MTRR_FIX4k_F0000 = 0x026E
AMD_MTRR_FIX4k_F8000 = 0x026F

AMD_MTRR_DEFTYPE = 0x02FF
    WB_DRAM_TYPE = 0x1E
    MTRR_DEF_TYPE_EN = 11
    MTRR_DEF_TYPE_FIX_EN = 10

HWCR = 0x0C0010015
    INVD_WBINVD = 0x04

IORR_BASE = 0x0C0010016

TOP_MEM = 0x0C001001A
TOP_MEM2 = 0x0C001001D

LS_CFG = 0x0C0011020
    DIS_SS = 28
    DIS_STREAM_ST = 28

IC_CFG = 0x0C0011021
    IC_DIS_SPEC_TLB_RLD = 9
    DIS_IND = 14
    DIS_I_CACHE = 14

DC_CFG = 0x0C0011022
    DC_DIS_SPEC_TLB_RLD = 4
    DIS_CLR_WBTOL2_SMC_HIT = 8
    DIS_HW_PF = 13

DE_CFG = 0x0C0011029
    CL_FLUSH_SERIALIZE = 23

BU_CFG2 = 0x0C001102A
CU_CFG2 = 0x0C001102A
    F10_CL_LINES_TO_NB_DIS = 15
    IC_DIS_SPEC_TLB_WR = 35

CU_CFG3 = 0x0C001102B
    COMBINE_CR0_CD = 49


CR0_PE = 1 # Protection Enable
CR0_NW = 29 # Not Write-through
CR0_CD = 30 # Cache Disable
CR0_PG = 31 # Paging Enable



CPUID_MODEL = 1
AMD_CPUID_FMF = 0x80000001
AMD_CPUID_APIC = 0x80000008

NB_CFG = 0x0C001001F
    INIT_APIC_ID_CPU_ID_LO = 54

MTRR_SYS_CFG = 0x0C0010010
  CHX_TO_DIRTY_DIS = 16
  SYS_UC_LOCK_EN = 17
  MTRR_FIX_DRAM_EN = 18
  MTRR_FIX_DRAM_MOD_EN = 19
  MTRR_VAR_DRAM_EN = 20
  MTRR_TOM2_EN = 21

PERF_CONTROL3 = 0x0C0010003
    PERF_CONTROL3_RESERVE_L = 0x00200000
    PERF_CONTROL3_RESERVE_H = 0x0FCF0
    CONFIG_EVENT_L = 0x0F0E2
    CONFIG_EVENT_H = 4

    EVENT_ENABLE = 22
PERF_COUNTER3 = 0x0C0010007

# Local use flags, in upper most byte if ESI
FLAG_UNKNOWN_FAMILY = 24 # Signals that the family# of the installed processor is not recognized
FLAG_STACK_REENTRY = 25 # Signals that the environment has made a re-entry (2nd) call to set up the stack
FLAG_IS_PRIMARY = 26 # Signals that this core is the primary within the comoute unit

CR0_MASK = ((1 << CR0_CD) | (1 << CR0_NW))
MSR_MASK = ((1 << MTRR_DEF_TYPE_EN)+(1 << MTRR_DEF_TYPE_FIX_EN))






.macro _WRMSR
        .byte 0x0f, 0x30
.endm

.macro _RDMSR
        .byte 0x0F, 0x32
.endm

.macro AMD_CPUID arg0
  .ifb \arg0
    mov $0x1, %eax
    .byte 0x0F, 0x0A2
    bswap %eax
    xchg %ah, %al
    rol $0x08, %eax
    and $0x0FFCF, ax
  .else
    mov \arg0, %eax
    .byte 0x0F, 0x0A2
  .endif
.endm
# 181 "src/vendorcode/amd/agesa/gcccar.inc"
.macro AMD_ENABLE_STACK_FAMILY_HOOK

    AMD_ENABLE_STACK_FAMILY_HOOK_F10
    AMD_ENABLE_STACK_FAMILY_HOOK_F12
    AMD_ENABLE_STACK_FAMILY_HOOK_F14
    AMD_ENABLE_STACK_FAMILY_HOOK_F15
.endm
# 201 "src/vendorcode/amd/agesa/gcccar.inc"
.macro AMD_DISABLE_STACK_FAMILY_HOOK

    AMD_DISABLE_STACK_FAMILY_HOOK_F10
    AMD_DISABLE_STACK_FAMILY_HOOK_F12
    AMD_DISABLE_STACK_FAMILY_HOOK_F14
    AMD_DISABLE_STACK_FAMILY_HOOK_F15

.endm
# 228 "src/vendorcode/amd/agesa/gcccar.inc"
.macro GET_NODE_ID_CORE_ID
    LOCAL node_core_exit

    mov $-1, %si
    GET_NODE_ID_CORE_ID_F10
    GET_NODE_ID_CORE_ID_F12
    GET_NODE_ID_CORE_ID_F14
    GET_NODE_ID_CORE_ID_F15



    cmp $-1, %si # Has family (node/core) already been discovered?
    jnz node_core_exit # Br if yes

   mov $((1 << FLAG_UNKNOWN_FAMILY)+(1 << FLAG_IS_PRIMARY)), %esi # No, Set error code, Only let BSP continue

    mov $APIC_BASE_ADDRESS, %ecx # MSR:0000_001B
    _RDMSR
    bt $APIC_BSC, %eax # Is this the BSC?
    jc node_core_exit # Br if yes
    hlt # Kill APs
node_core_exit:

.endm
# 280 "src/vendorcode/amd/agesa/gcccar.inc"
.macro AMD_ENABLE_STACK_FAMILY_HOOK_F10
    LOCAL fam10_enable_stack_hook_exit

    AMD_CPUID $CPUID_MODEL
    shr $20, %eax # AL = cpu extended family
    cmp $0x01, %al # Is this family 10h?
    jnz fam10_enable_stack_hook_exit # Br if no

    mov $DC_CFG, %ecx # MSR:C001_1022
    _RDMSR
    bts $DC_DIS_SPEC_TLB_RLD, %eax # Turn on Disable speculative DTLB reloads bit
    bts $DIS_CLR_WBTOL2_SMC_HIT, %eax # Turn on Disable the self modifying code check buffer bit
    bts $DIS_HW_PF, %eax # Turn on Disable hardware prefetches bit
    _WRMSR

    dec %cx # MSR:C001_1021
    _RDMSR
    bts $IC_DIS_SPEC_TLB_RLD, %eax # Turn on Disable speculative TLB reloads bit
    bts $DIS_IND, %eax # Turn on Disable indirect branch predictor
    _WRMSR

    mov $BU_CFG2, %ecx # MSR C001_102A
    _RDMSR
    bts $F10_CL_LINES_TO_NB_DIS, %eax # Allow BIOS ROM to be cached in the IC
    bts $(IC_DIS_SPEC_TLB_WR-32), %edx #Disable speculative writes to the ITLB
    _WRMSR

    mov $HWCR, %ecx # MSR C001_0015
    _RDMSR
    bt $FLAG_STACK_REENTRY, %esi # Check if stack has already been set
    jc fam10_skipClearingBit4
    btr $INVD_WBINVD, %eax # disable INVD -> WBINVD conversion
    _WRMSR

fam10_skipClearingBit4:
    mov %esi, %eax # load core#
    or %al, %al # If (BSP)
    jne fam10_enable_stack_hook_exit
    mov $PERF_COUNTER3, %ecx # Select performance counter three
                                        # to count number of CAR evictions
    xor %eax, %eax # Initialize the lower part of the counter to zero
    xor %edx, %edx # Initializa the upper part of the counter to zero
    _WRMSR # Save it
    mov $PERF_CONTROL3, %ecx # Select the event control three
    _RDMSR # Get the current setting
    and $PERF_CONTROL3_RESERVE_L, %eax # Preserve the reserved bits
    or $CONFIG_EVENT_L, %eax # Set the lower part of event register to
                                        # select CAR Corruption occurred by any cores
    and $PERF_CONTROL3_RESERVE_H, %dx # Preserve the reserved bits
    or $CONFIG_EVENT_H, %dx # Set the upper part of event register
    _WRMSR # Save it
    bts $EVENT_ENABLE, %eax # Enable it
    _WRMSR # Save it

fam10_enable_stack_hook_exit:
.endm
# 361 "src/vendorcode/amd/agesa/gcccar.inc"
.macro AMD_DISABLE_STACK_FAMILY_HOOK_F10
    LOCAL fam10_disable_stack_hook_exit

    AMD_CPUID CPUID_MODEL
    shr $20, %eax # AL = cpu extended family
    cmp $0x01, %al # Is this family 10h?
    jnz fam10_disable_stack_hook_exit # Br if no

    mov $DC_CFG, %ecx # MSR:C001_1022
    _RDMSR
    btr $DC_DIS_SPEC_TLB_RLD, %eax # Enable speculative TLB reloads
    btr $DIS_CLR_WBTOL2_SMC_HIT, %eax # Allow self modifying code check buffer
    btr $DIS_HW_PF, %eax # Allow hardware prefetches
    _WRMSR

    dec %cx # MSR:C001_1021
    _RDMSR
    btr $DIS_IND, %eax # Turn on indirect branch predictor
    btr $IC_DIS_SPEC_TLB_RLD, %eax # Turn on speculative TLB reloads
    _WRMSR

    mov $BU_CFG2, %ecx # MSR:C001_102A
    _RDMSR
    btr $F10_CL_LINES_TO_NB_DIS, %eax # Return L3 to normal mode
    btr $(IC_DIS_SPEC_TLB_WR-32), %edx #Re-enable speculative writes to the ITLB
    _WRMSR

    #--------------------------------------------------------------------------
    # Begin critical sequence in which EAX, BX, ECX, and EDX must be preserved.
    #--------------------------------------------------------------------------

    mov $HWCR, %ecx # MSR:0000_0015
    _RDMSR
    mov %ax, %bx # Save INVD -> WBINVD bit
    btr $INVD_WBINVD, %eax # Disable INVD -> WBINVD conversion for the invd instruction.
    _WRMSR
    invd # Clear the cache tag RAMs
    mov %bx, %ax # Restore INVD -> WBINVD bit
    _WRMSR

    #--------------------------------------------------------------------------
    # End critical sequence in which EAX, BX, ECX, and EDX must be preserved.
    #--------------------------------------------------------------------------

    mov $PERF_CONTROL3, %ecx # Select the event control three
    _RDMSR # Retrieve the current value
    btc $EVENT_ENABLE, %eax # Is event enable, complement it as well
    jnc fam10_disable_stack_hook_exit # No
    cmp $CONFIG_EVENT_L, %ax # Is the lower part of event set to capture the CAR Corruption
    jne fam10_disable_stack_hook_exit # No
    cmp $CONFIG_EVENT_H, %dl # Is the upper part of event set to capture the CAR Corruption
    jne fam10_disable_stack_hook_exit # No
    _WRMSR # Disable the event

fam10_disable_stack_hook_exit:
.endm
# 430 "src/vendorcode/amd/agesa/gcccar.inc"
.macro GET_NODE_ID_CORE_ID_F10

    LOCAL node_core_f10_exit
    LOCAL node_core_f10_AP

    cmp $-1, %si # Has node/core already been discovered?
    jnz node_core_f10_exit # Br if yes

    AMD_CPUID $CPUID_MODEL
    shr $20, %eax # AL = cpu extended family
    cmp $0x01, %al # Is this family 10h?
    jnz node_core_f10_exit # Br if no

    xor %esi, %esi # Assume BSC, clear flags
    mov $APIC_BASE_ADDRESS, %ecx # MSR:0000_001B
    _RDMSR
    bt $APIC_BSC, %eax # Is this the BSC?
    jnc node_core_f10_AP # Br if no

        # This is the BSP.
    # Enable routing tables on BSP (just in case the HT init code has not yet enabled them)
    mov $0x8000C06C, %eax # PCI address for D18F0x6C Link Initialization Control Register
    mov $0x0CF8, %dx
    out %eax, %dx
    add $4, %dx
    in %dx, %eax
    btr $0, %eax # Set LinkInitializationControl[RouteTblDis] = 0
    out %eax, %dx
    jmp 1f #

node_core_f10_AP:

    # This is an AP. Routing tables have been enabled by the HT Init process.
    # Also, the MailBox register was set by the BSP during early init
    # The Mailbox register content is formatted as follows:
    # UINT32 Node:4#
    # UINT32 Socket:4#
    # UINT32 Module:2#
    # UINT32 ModuleType:2#
    # UINT32 :20#

    mov $0x0C0000408, %ecx # Read the family 10h mailbox
    _RDMSR # MC4_MISC1[63:32]
    mov %dx, %si # SI = raw mailbox contents (will extract node# from this)
    shr $24, %ebx # BL = CPUID Fn0000_0001_EBX[LocalApicId]
    mov %bx, %di # DI = Initial APIC ID (will extract core# from this)

    AMD_CPUID $AMD_CPUID_APIC #
    shr $4, %ch # CH = ApicIdSize, #bits in APIC ID that show core#
    inc %cl # CL = Number of enabled cores in the socket
    mov %cx, %bx

    mov $NB_CFG, %ecx # MSR:C001_001F
    _RDMSR # EDX has InitApicIdCpuIdLo bit

    mov %bh, %cl # CL = APIC ID size
    mov $1, %al # Convert APIC ID size to an AND mask
    shl %cl, %al # AL = 2^APIC ID size
    dec %al # AL = mask for relative core number
    xor %ah, %ah # AX = mask for relative core number
    bt $(INIT_APIC_ID_CPU_ID_LO-32), %edx # InitApicIdCpuIdLo == 1?
    #.if (!carry?) # Br if yes
    jc 0f
        mov $8, %ch # Calculate core number shift count
        sub %cl, %ch # CH = core shift count
        mov %ch, %cl
        shr %cl, %di # Right justify core number
    #.endif
   0:
    and %ax, %di # DI = socket-relative core number

    mov %si, %cx # CX = raw mailbox value
    shr $10, %cx # CL[1:0] = ModuleType or #nodes per socket (0-SCM, 1-MCM)
    and $3, %cl # Isolate ModuleType
    xor %bh, %bh # BX = Number of enabled cores in the socket
    shr %cl, %bx # BX = Number of enabled cores per node
    xor %dx, %dx # Clear upper word for div
    mov %di, %ax # AX = socket-relative core number
    div %bx # DX = node-relative core number
    movzx %si, %eax # prepare return value, [23:16]=shared Core# (=0, not shared)
    and $0x000F, %ax # AX = node number
    shl $8, %ax # [15:8]=node#
    mov %dl, %al # [7:0]=core# (relative to node)
    mov %eax, %esi # ESI = return value
1:
 bts $FLAG_IS_PRIMARY, %esi # all Family 10h cores are primary
node_core_f10_exit:
.endm
# 547 "src/vendorcode/amd/agesa/gcccar.inc"
.macro AMD_ENABLE_STACK_FAMILY_HOOK_F12
    LOCAL fam12_enable_stack_hook_exit

    AMD_CPUID $CPUID_MODEL
    shr $20, %eax # AL = cpu extended family
    cmp $0x03, %al # Is this family 12h?
    jnz fam12_enable_stack_hook_exit # Br if no

    mov $DC_CFG, %ecx # MSR:C001_1022
    _RDMSR
    bts $DC_DIS_SPEC_TLB_RLD, %eax # Disable speculative DC-TLB reloads
    bts $DIS_CLR_WBTOL2_SMC_HIT, %eax # Disable self modifying code check buffer
    bts $DIS_HW_PF, %eax # Disable hardware prefetches
    _WRMSR

    dec %cx #IC_CFG # MSR:C001_1021
    _RDMSR
    bts $IC_DIS_SPEC_TLB_RLD, %eax # Disable speculative IC-TLB reloads
    _WRMSR

    dec %cx #LS_CFG # MSR:C001_1020
    _RDMSR
    bts $DIS_SS, %eax # Disabled Streaming store functionality
    _WRMSR

    mov $HWCR, %ecx # MSR C001_0015
    _RDMSR
    bt $FLAG_STACK_REENTRY , %esi # Check if stack has already been set
    jc fam12_skipClearingBit4
    btr $INVD_WBINVD, %eax # disable INVD -> WBINVD conversion
    _WRMSR

fam12_skipClearingBit4:
    mov $DE_CFG, %ecx # MSR:C001_1029
    _RDMSR
    bts $CL_FLUSH_SERIALIZE, %eax # Serialize all CL Flush actions
    _WRMSR

fam12_enable_stack_hook_exit:
.endm
# 610 "src/vendorcode/amd/agesa/gcccar.inc"
.macro AMD_DISABLE_STACK_FAMILY_HOOK_F12
    LOCAL fam12_disable_stack_hook_exit

    AMD_CPUID $CPUID_MODEL
    shr $20, %eax # AL = cpu extended family
    cmp $0x03, %al # Is this family 12h?
    jnz fam12_disable_stack_hook_exit # Br if no

    mov $DC_CFG, %ecx # MSR:C001_1022
    _RDMSR
    btr $DC_DIS_SPEC_TLB_RLD, %eax # Turn on speculative DC-TLB reloads
    btr $DIS_CLR_WBTOL2_SMC_HIT, %eax # Enable self modifying code check buffer
    btr $DIS_HW_PF, %eax # Enable Hardware prefetches
    _WRMSR

    dec %cx #IC_CFG # MSR:C001_1021
    _RDMSR
    btr $IC_DIS_SPEC_TLB_RLD, %eax # Turn on speculative IC-TLB reloads
    _WRMSR

    dec %cx #LS_CFG # MSR:C001_1020
    _RDMSR
    btr $DIS_SS, %eax # Turn on Streaming store functionality
    _WRMSR

    mov $DE_CFG, %ecx # MSR:C001_1029
    _RDMSR
    btr $CL_FLUSH_SERIALIZE, %eax
    _WRMSR

    #--------------------------------------------------------------------------
    # Begin critical sequence in which EAX, BX, ECX, and EDX must be preserved.
    #--------------------------------------------------------------------------

    mov $HWCR, %ecx # MSR:0000_0015h
    _RDMSR
    mov %ax, %bx # Save INVD -> WBINVD bit
    btr $INVD_WBINVD, %eax # Disable INVD -> WBINVD conversion
    _WRMSR
    invd # Clear the cache tag RAMs
    mov %bx, %ax # Restore INVD -> WBINVD bit
    _WRMSR

    #--------------------------------------------------------------------------
    # End critical sequence in which EAX, BX, ECX, and EDX must be preserved.
    #--------------------------------------------------------------------------

fam12_disable_stack_hook_exit:
.endm
# 672 "src/vendorcode/amd/agesa/gcccar.inc"
.macro GET_NODE_ID_CORE_ID_F12

    LOCAL node_core_f12_exit

    cmp $-1, %si # Has node/core already been discovered?
    jnz node_core_f12_exit # Br if yes

    AMD_CPUID $CPUID_MODEL
    shr $20, %eax # AL = cpu extended family
    cmp $0x03, %al # Is this family 12h?
    jnz node_core_f12_exit # Br if no

    shr $24, %ebx # CPUID_0000_0001_EBX[31:24]: initial local APIC physical ID
    bts $FLAG_IS_PRIMARY, %ebx # all family 12h cores are primary
    mov %ebx, %esi # ESI = Node#=0, core number
node_core_f12_exit:
.endm
# 713 "src/vendorcode/amd/agesa/gcccar.inc"
.macro AMD_ENABLE_STACK_FAMILY_HOOK_F14
    LOCAL fam14_enable_stack_hook_exit

    AMD_CPUID $CPUID_MODEL
    shr $20, %eax # AL = cpu extended family
    cmp $0x05, %al # Is this family 14h?
    jnz fam14_enable_stack_hook_exit # Br if no

    mov $DC_CFG, %ecx # MSR:C001_1022
    _RDMSR
    bts $DIS_HW_PF, %eax # Disable hardware prefetches
    _WRMSR

    dec %cx #IC_CFG # MSR:C001_1021
    _RDMSR
    bts $IC_DIS_SPEC_TLB_RLD, %eax # Disable speculative TLB reloads
    _WRMSR

    dec %cx #LS_CFG # MSR:C001_1020
    _RDMSR
    bts $DIS_STREAM_ST, %eax # Disabled Streaming store functionality
    _WRMSR

    mov $HWCR, %ecx # MSR C001_0015
    _RDMSR
    bt $FLAG_STACK_REENTRY, %esi # Check if stack has already been set
    jc fam14_skipClearingBit4
    btr $INVD_WBINVD, %eax # Disable INVD -> WBINVD conversion
    _WRMSR
fam14_skipClearingBit4: # Keeping this label

fam14_enable_stack_hook_exit:
.endm
# 766 "src/vendorcode/amd/agesa/gcccar.inc"
.macro AMD_DISABLE_STACK_FAMILY_HOOK_F14
    LOCAL fam14_disable_stack_hook_exit

    AMD_CPUID $CPUID_MODEL
    shr $20, %eax # AL = cpu extended family
    cmp $0x05, %al # Is this family 14h?
    jnz fam14_disable_stack_hook_exit # Br if no

    mov $LS_CFG, %ecx # MSR:C001_1020
    _RDMSR
    btr $DIS_STREAM_ST, %eax # Turn on Streaming store functionality
    _WRMSR

    inc %cx #IC_CFG # MSR:C001_1021
    _RDMSR
    btr $IC_DIS_SPEC_TLB_RLD, %eax # Turn on speculative DC-TLB reloads
    _WRMSR

    inc %cx #DC_CFG # MSR:C001_1022
    _RDMSR
    btr $DIS_HW_PF, %eax # Turn on hardware prefetches
    _WRMSR

    #--------------------------------------------------------------------------
    # Begin critical sequence in which EAX, BX, ECX, and EDX must be preserved.
    #--------------------------------------------------------------------------

    mov $HWCR, %ecx # MSR:C001_0015h
    _RDMSR
    btr $INVD_WBINVD, %eax # Disable INVD -> WBINVD conversion
    _WRMSR
    invd # Clear the cache tag RAMs
    bts $INVD_WBINVD, %eax # Turn on Conversion of INVD to WBINVD
    _WRMSR

    #--------------------------------------------------------------------------
    # End critical sequence in which EAX, BX, ECX, and EDX must be preserved.
    #--------------------------------------------------------------------------

fam14_disable_stack_hook_exit:
.endm
# 820 "src/vendorcode/amd/agesa/gcccar.inc"
.macro GET_NODE_ID_CORE_ID_F14

    LOCAL node_core_f14_exit

    cmp $0x-1, %si # Has node/core already been discovered?
    jnz node_core_f14_exit # Br if yes

    AMD_CPUID $CPUID_MODEL
    shr $20, %eax # AL = cpu extended family
    cmp $0x05, %al # Is this family 14h?
    jnz node_core_f14_exit # Br if no

    xor %esi, %esi # Node must be 0
    bts $FLAG_IS_PRIMARY, %esi # all family 14h cores are primary
    mov $APIC_BASE_ADDRESS, %ecx # MSR:0000_001B
    _RDMSR
    bt $APIC_BSC, %eax # Is this the BSC?
    jc node_core_f14_exit # Br if yes
    inc %si # Set core to 1
node_core_f14_exit:
.endm
# 868 "src/vendorcode/amd/agesa/gcccar.inc"
.macro AMD_ENABLE_STACK_FAMILY_HOOK_F15
    LOCAL fam15_enable_stack_hook_exit

    AMD_CPUID $CPUID_MODEL
    shr $20, %eax # AL = cpu extended family
    cmp $0x06, %al # Is this family 15h?
    jnz fam15_enable_stack_hook_exit # Br if no

    bt $FLAG_STACK_REENTRY , %esi # Check if stack has already been set
    jc fam15_skipClearingBit4
    mov $HWCR, %ecx # MSR C001_0015
    _RDMSR
    btr $INVD_WBINVD, %eax # disable INVD -> WBINVD conversion
    _WRMSR

fam15_skipClearingBit4:
    mov $LS_CFG, %ecx # MSR:C001_1020
    _RDMSR
    bts $DIS_SS, %eax # Turn on Streaming store functionality disabled bit
    _WRMSR

    inc %ecx #IC_CFG # MSR:C001_1021
    _RDMSR
    bts $IC_DIS_SPEC_TLB_RLD, %eax # Turn on Disable speculative IC-TLB reloads bit
    _WRMSR

    inc %ecx #DC_CFG # MSR:C001_1022
    _RDMSR
    bts $DC_DIS_SPEC_TLB_RLD, %eax # Turn on Disable speculative DC-TLB reloads bit
    bts $DIS_HW_PF, %eax # Turn on Disable hardware prefetches bit
    _WRMSR

    mov $CU_CFG3, %ecx # MSR:C001_102B
    _RDMSR
    btr $(COMBINE_CR0_CD - 32), %edx # Clear CombineCr0Cd bit
    _WRMSR

fam15_enable_stack_hook_exit:
.endm
# 929 "src/vendorcode/amd/agesa/gcccar.inc"
.macro AMD_DISABLE_STACK_FAMILY_HOOK_F15
    LOCAL fam15_disable_stack_hook_exit

    AMD_CPUID $CPUID_MODEL
    mov %eax, %ebx # Save revision info to EBX
    shr $20, %eax # AL = cpu extended family
    cmp $0x06, %al # Is this family 15h?
    jnz fam15_disable_stack_hook_exit # Br if no

    mov $LS_CFG, %ecx # MSR:C001_1020
    #.if (ebx != 00600F00h) ; Is this rev A0?
    cmp $0x00600F00, %ebx
    jz 0f
    _RDMSR
    btr $DIS_SS, %eax # Turn on Streaming store functionality
    _WRMSR
    #.endif
    0: # End workaround for errata 495 and 496

    inc %ecx #IC_CFG # MSR:C001_1021
    _RDMSR
    btr $IC_DIS_SPEC_TLB_RLD, %eax # Turn on speculative TLB reloads
    _WRMSR

    inc %ecx #DC_CFG # MSR:C001_1022
    _RDMSR
    btr $DC_DIS_SPEC_TLB_RLD, %eax # Turn on speculative TLB reloads
    #.if (ebx != 00600F00h) # Is this rev A0?
    cmp $0x00600F00, %ebx
    jz 0f
    btr $DIS_HW_PF, %eax # Turn on hardware prefetches
    #.endif # End workaround for erratum 498
    0:
    _WRMSR
    #--------------------------------------------------------------------------
    # Begin critical sequence in which EAX, BX, ECX, and EDX must be preserved.
    #--------------------------------------------------------------------------

    bt $FLAG_IS_PRIMARY, %esi
    #.if (carry?) # Only clear cache from primary core
    jnc 0f
    mov $HWCR, %ecx # MSR:C001_0015h
    _RDMSR
    btr $INVD_WBINVD, %eax # Disable INVD -> WBINVD conversion
    _WRMSR
    invd # Clear the cache tag RAMs
    bts $INVD_WBINVD, %eax # Turn on Conversion of INVD to WBINVD
    _WRMSR
    #.endif # end
    0:

    #--------------------------------------------------------------------------
    # End critical sequence in which EAX, BX, ECX, and EDX must be preserved.
    #--------------------------------------------------------------------------

    mov $CU_CFG3, %ecx # MSR:C001_102B
    _RDMSR
    bts $(COMBINE_CR0_CD - 32), %eax # Set CombineCr0Cd bit
    _WRMSR

fam15_disable_stack_hook_exit:
.endm
# 1005 "src/vendorcode/amd/agesa/gcccar.inc"
.macro GET_NODE_ID_CORE_ID_F15

    LOCAL node_core_f15_exit
    LOCAL node_core_f15_AP
    LOCAL node_core_f15_shared

    cmp $-1, %si # Has node/core already been discovered?
    jnz node_core_f15_exit # Br if yes

    AMD_CPUID $CPUID_MODEL
    shr $20, %eax # AL = cpu extended family
    cmp $06, %al # Is this family 15h?
    jnz node_core_f15_exit # Br if no

    xor %esi, %esi # Assume BSC, clear local flags
    mov $APIC_BASE_ADDRESS, %ecx # MSR:0000_001B
    _RDMSR
    bt $APIC_BSC, %eax # Is this the BSC?
    jnc node_core_f15_AP # Br if no

    # This is the BSP.
    # Enable routing tables on BSP (just in case the HT init code has not yet enabled them)
    mov $0x8000C06C, %eax # PCI address for D18F0x6C Link Initialization Control Register
    mov $0x0CF8, %dx
    out %eax, %dx
    add $4, %dx
    in %dx, %eax
    btr $0, %eax # Set LinkInitializationControl[RouteTblDis] = 0
    out %eax, %dx
    jmp node_core_f15_shared #

node_core_f15_AP:

    # This is an AP. Routing tables have been enabled by the HT Init process.
    # Also, the MailBox register was set by the BSP during early init
    # The Mailbox register content is formatted as follows:
    # UINT32 Node:4;
    # UINT32 Socket:4;
    # UINT32 Module:2;
    # UINT32 ModuleType:2;
    # UINT32 :20;

    mov $0x0C0000408, %ecx # Read the family 15h mailbox
    _RDMSR # MC4_MISC1[63:32]
    mov %dx, %si # SI = raw mailbox contents (will extract node# from this)
    shr $24, %ebx # BL = CPUID Fn0000_0001_EBX[LocalApicId]
    mov %bx, %di # DI = Initial APIC ID (will extract core# from this)

    AMD_CPUID $AMD_CPUID_APIC #
    shr $4, %ch # CH = ApicIdSize, #bits in APIC ID that show core#
    inc %cl # CL = Number of enabled cores in the socket
    mov %cx, %bx

    mov $NB_CFG, %ecx
    _RDMSR # EDX has InitApicIdCpuIdLo bit

    mov %bh, %cl # CL = APIC ID size
    mov $1, %al # Convert APIC ID size to an AND mask
    shl %cl, %al # AL = 2^APIC ID size
    dec %al # AL = mask for relative core number
    xor %ah, %ah # AX = mask for relative core number
    bt $(INIT_APIC_ID_CPU_ID_LO-32), %edx # InitApicIdCpuIdLo == 1?
    #.if (!carry?) # Br if yes
    jc 0f
        mov $8, %ch # Calculate core number shift count
        sub %cl, %ch # CH = core shift count
        mov %ch, %cl
        shr %cl, %di # Right justify core number
    #.endif
    0:
    and %ax, %di # DI = socket-relative core number

    mov %si, %cx # CX = raw mailbox value
    shr $10, %cx # CL[1:0] = ModuleType or #nodes per socket (0-SCM, 1-MCM)
    and $3, %cl # Isolate ModuleType
    xor %bh, %bh # BX = Number of enabled cores in the socket
    shr %cl, %bx # BX = Number of enabled cores per node
    xor %dx, %dx # Clear upper word for div
    mov %di, %ax # AX = socket-relative core number
    div %bx # DX = node-relative core number
    movzx %si, %eax # Prepare return value
    and $0x000F, %ax # AX = node number
    shl $8,%ax # [15:8]=node#
    mov %dl, %al # [7:0]=core# (relative to node)
    mov %eax, %esi # ESI = node-relative core number


      # determine if this core shares MTRRs

node_core_f15_shared:
    mov $0x8000C580, %eax # Compute Unit Status
    mov %si, %bx
    shl $3, %bh # Move node# to PCI Dev# field
    add %bh, %ah # Adjust for node number
    mov $0x0CF8, %dx
    out %eax, %dx
    add $4, %dx
    in %dx, %eax # [3:0]=Enabled# [19:16]=DualCore

                                        # BL is MyCore#
    mov $0x06, %cx # Use CH as 'first of pair' core#
    #.while (cl > 0)
    jmp 0f
    8:
        bt $0, %eax # Is pair enabled?
        #.if (carry?) #
        jnc 1f
            mov $0x01, %bh # flag core as primary
            bt $16, %eax # Is there a 2nd in the pair?
            #.if (carry?) #
            jnc 4f
                #.break .if (ch == bl) # Does 1st match MyCore#?
                cmp %bl, %ch
                je 9f
                inc %ch
                xor %bh, %bh # flag core as NOT primary
                #.break .if (ch == bl) # Does 2nd match MyCore#?
                cmp %bl, %ch
                je 9f
                jmp 2f
            #.else # No 2nd core
            4:
                #.break .if (ch == bl) # Does 1st match MyCore#?
                cmp %bl, %ch
                je 9f
            #.endif
            2:
            inc %ch
        #.endif
        1:
        shr $1, %eax
        dec %cl
    #.endw
    0:
    #.if (cl == 0)
    cmp $0x0, %cl
    ja 8b
    9:
    or %cl, %cl
    jne 1f
        #Error - core# didn't match Compute Unit Status content
        bts $FLAG_UNKNOWN_FAMILY, %esi
        bts $FLAG_IS_PRIMARY, %esi # Set Is_Primary for unknowns
    #.endif
    1:
    #.if (bh != 0) # Check state of primary for the matched core
    or %bh, %bh
    je 2f
        bts $FLAG_IS_PRIMARY, %esi # Set shared flag into return value
    #.endif
    2:

node_core_f15_exit:

.endm
# 1229 "src/vendorcode/amd/agesa/gcccar.inc"
.macro AMD_ENABLE_STACK

# These are local labels. Declared so linker doesn't cause 'redefined label' errors
    LOCAL SetupStack
    LOCAL Real16bMode
    LOCAL Protected32Mode
    LOCAL ClearTheStack

# Note that SS:ESP will be default stack. Note that this stack
# routine will not be used after memory has been initialized. Because
# of its limited lifetime, it will not conflict with typical PCI devices.
    movd %ebx, %mm0 # Put return address in a safe place
    movd %ebp, %mm1 # Save some other user registers

    # get node id and core id of current executing core
    GET_NODE_ID_CORE_ID # Sets ESI[23:16]=Shared core## SI[15,8]= Node## SI[7,0]= core# (relative to node)
    # Note: ESI[31:24] are used for flags: Unrecognized Family, Is_Primary core, Stack already established

    # determine if stack is already enabled. We are using the DefType MSR for this determination.
    # It is =0 after reset; CAR setup sets it to enable the MTRRs
    mov %cr0, %eax
    test $CR0_MASK, %eax # Is cache disabled? (CD & NW bits)
    jnz SetupStack # Jump if yes
    mov $AMD_MTRR_DEFTYPE, %ecx # MSR:0000_02FF
    _RDMSR
    test $MSR_MASK, %eax # Are the default types enabled? (MTRR_DEF_TYPE_EN + MTRR_DEF_TYPE_FIX_EN)
    jz SetupStack # Jump if no
    or $FLAG_STACK_REENTRY, %esi # Bit25, indicate stack has already been initialized

SetupStack:
    # Set node to map the first 16MB to node 0# 0000_0000 to 00FF_FFFF as DRAM
    mov %esi, %ebx # Get my Node/Core info
    xor %bl, %bl
    shl $3, %bh # Isolate my node#, match alignment for PCI Dev#
    mov $0x8000C144, %eax # D18F1x44:DRAM Base/Limit# N is Base, N+4 is Limit
    add %bh, %ah
    mov %eax, %ebx # Save PCI address for Base/Limit pair

    mov $0x0CF8, %dx
    out %eax, %dx
    add $4, %dx
    xor %eax, %eax # Least Significant bit is AD24 so 0 sets mask of 00FF_FFFF (16MB)
    out %eax, %dx # DRAM Limit = node0, no interleave

    mov %ebx, %eax
    sub $4, %eax # Now point to the Base register
    mov $0x0CF8, %dx
    out %eax, %dx
    add $4, %dx
    mov $0x00000003, %eax # Set the read and write enable bits
    out %eax, %dx # DRAM Base = 0x0000, R/W

    AMD_ENABLE_STACK_FAMILY_HOOK

    # Init CPU MSRs for our init routines
    mov $MTRR_SYS_CFG, %ecx # SYS_CFG
    _RDMSR
    bts $MTRR_FIX_DRAM_MOD_EN, %eax # Turn on modification enable bit
    _WRMSR

    mov %esi, %eax
    bt $FLAG_STACK_REENTRY, %eax # Is this a 2nd entry?
    #.if (!carry?) # On a re-entry, do not clear MTRRs or reset TOM; just reset the stack SS:ESP
    jc 0f
        bt $FLAG_IS_PRIMARY, %eax # Is this core the primary in a compute unit?
        #.if (carry?) # Families using shared groups do not need to clear the MTRRs since that is done at power-on reset
            # Note: Relying on MSRs to be cleared to 0's at reset for families w/shared cores
            # Clear all variable and Fixed MTRRs for non-shared cores
        jnc 0f
        mov $AMD_MTRR_VARIABLE_BASE0, %ecx
        xor %eax, %eax
        xor %edx, %edx
        #.while (cl != 10h) # Variable MTRRphysBase[n] and MTRRphysMask[n]
        jmp 1f
        2:
            _WRMSR
            inc %cl
        #.endw
        1:
        cmp $0x10, %cl
        jne 2b
        mov $AMD_MTRR_FIX64k_00000, %cx # MSR:0000_0250
        _WRMSR
        mov $AMD_MTRR_FIX16k_80000, %cx # MSR:0000_0258
        _WRMSR
        mov $AMD_MTRR_FIX16k_A0000, %cx # MSR:0000_0259
        _WRMSR
        mov $AMD_MTRR_FIX4k_C0000, %cx # Fixed 4Ks: MTRRfix4K_C0000 to MTRRfix4K_F8000
        #.while (cl != 70h)
        jmp 3f
        4:
            _WRMSR
            inc %cl
        #.endw
        3:
        cmp $0x70, %cl
        jne 4b
        # Set TOP_MEM (C001_001A) for non-shared cores to 16M. This will be increased at heap init.
        # - not strictly needed since the FixedMTRRs take presedence.
        mov $(16 * 1024 * 1024), %eax
        mov $TOP_MEM, %ecx # MSR:C001_001A
        _WRMSR
        #.endif # End Is_Primary
    #.endif # End Stack_ReEntry
    0:
    # Clear IORRs (C001_0016-19) and TOM2(C001_001D) for all cores
    xor %eax, %eax
    xor %edx, %edx
    mov $IORR_BASE, %ecx # MSR:C001_0016 - 0019
    #.while (cl != 1Ah)
    jmp 1f
    2:
        _WRMSR
        inc %cl
    #.endw
    1:
    cmp $0x1A, %cl
    jne 2b
    mov $TOP_MEM2, %ecx # MSR:C001_001D
    _WRMSR

    # setup MTTRs for stacks
    # A speculative read can be generated by a speculative fetch mis-aligned in a code zone
    # or due to a data zone being interpreted as code. When a speculative read occurs outside a
    # controlled region (intentionally used by software), it could cause an unwanted cache eviction.
    # To prevent speculative reads from causing an eviction, the unused cache ranges are set
    # to UC type. Only the actively used regions (stack, heap) are reflected in the MTRRs.
    # Note: some core stack regions will share an MTRR since the control granularity is much
    # larger than the allocated stack zone. The allocation algorithm must account for this 'extra'
    # space covered by the MTRR when parseling out cache space for the various uses. In some cases
    # this could reduce the amount of EXE cache available to a core. see cpuCacheInit.c

    # Outcome of this block is that: (Note the MTRR map at the top of the file)
    # ebp - start address of stack block
    # ebx - [31:16] - MTRR MSR address
    # - [15:8] - slot# in MTRR register
    # - [7:0] - block size in #4K blocks
    # review: ESI[31:24]=Flags; SI[15,8]= Node#; SI[7,0]= core# (relative to node)


    mov %si, %ax # Load node, core
    #.if (al == 0) # Is a core 0?
    or %al, %al
    jne 1f
        #.if (ah == 0) # Is Node 0? (BSP)
        or %ah, %ah
        jne 2f
            # Is BSP, assign a 64K stack
            mov $((AMD_MTRR_FIX64k_00000 << 16) + (3 << 8) + (BSP_STACK_SIZE / 0x1000)), %ebx
            mov $BSP_STACK_BASE_ADDR, %ebp
            jmp 0f
        #.else # node 1 to 7, core0
        2:
            # Is a Core0 of secondary node, assign 16K stacks
            mov $AMD_MTRR_FIX16k_80000, %bx
            shl $16, %ebx #
            mov %ah, %bh # Node# is used as slot#
            mov $(CORE0_STACK_SIZE / 0x1000), %bl
            mov %ah, %al # Base = (Node# * Size)#
            mul %bl #
            movzx %ax, %eax #
            shl $12, %eax # Expand back to full byte count (* 4K)
            add $CORE0_STACK_BASE_ADDR, %eax
            mov %eax, %ebp
        #.endif
        jmp 0f
    #.else #core 1 thru core 7
    1:
        # Is core 1-7 of any node, assign 4K stacks
        mov $8, %al # CoreIndex = ( (Node# * 8) ...
        mul %ah #
        mov %si, %bx #
        add %bl, %al # ... + Core#)#

        mov $AMD_MTRR_FIX64k_00000, %bx
        shl $16, %ebx #
        mov %al, %bh # Slot# = (CoreIndex / 16) + 4#
        shr $4, %bh #
        add $4, %bh #
        mov $(CORE1_STACK_SIZE / 0x1000), %bl

        mul %bl # Base = ( (CoreIndex * Size) ...
        movzx %ax, %eax #
        shl $12, %eax # Expand back to full byte count (* 4K)
        add $CORE1_STACK_BASE_ADDR, %eax # ... + Base_Addr)#
        mov %eax, %ebp
    #.endif
    0:

    # Now set the MTRR. Add this to already existing settings (don't clear any MTRR)
    mov $WB_DRAM_TYPE, %edi # Load Cache type in 1st slot
    mov %bh, %cl # ShiftCount = ((slot# ...
    and $0x03, %cl # ... % 4) ...
    shl $0x03, %cl # ... * 8)#
    shl %cl, %edi # Cache type is now in correct position
    ror $16, %ebx # Get the MTRR address
    movzx %bx, %ecx #
    rol $16, %ebx # Put slot# & size back in BX
    _RDMSR # Read-modify-write the MSR
    #.if (bh < 4) # Is value in lower or upper half of MSR?
    cmp $4, %bh
    jae 1f
        or %edi, %eax #
        jmp 0f
    #.else
    1: #
        or %edi, %edx #
    #.endif #
    0:
    _WRMSR #

    # Enable MTRR defaults as UC type
    mov $AMD_MTRR_DEFTYPE, %ecx # MSR:0000_02FF
    _RDMSR # Read-modify-write the MSR
    bts $MTRR_DEF_TYPE_EN, %eax # MtrrDefTypeEn
    bts $MTRR_DEF_TYPE_FIX_EN, %eax # MtrrDefTypeFixEn
    _WRMSR

    # Close the modification window on the Fixed MTRRs
    mov $MTRR_SYS_CFG, %ecx # MSR:0C001_0010
    _RDMSR
    bts $MTRR_FIX_DRAM_EN, %eax # MtrrFixDramEn
    bts $MTRR_VAR_DRAM_EN, %eax # variable MTRR enable bit
    btr $MTRR_FIX_DRAM_MOD_EN, %eax # Turn off modification enable bit
    _WRMSR

    # Enable caching in CR0
    mov %cr0, %eax # Enable WT/WB cache
    btr $CR0_PG, %eax # Make sure paging is disabled
    btr $CR0_CD, %eax # Clear CR0 NW and CD
    btr $CR0_NW, %eax
    mov %eax, %cr0

    # Use the Stack Base & size to calculate SS and ESP values
    # review:
    # esi[31:24]=Flags; esi[15,8]= Node#; esi[7,0]= core# (relative to node)
    # ebp - start address of stack block
    # ebx - [31:16] - MTRR MSR address
    # - [15:8] - slot# in MTRR register
    # - [7:0] - block size in #4K blocks

    mov %ebp, %esp # Initialize the stack pointer
    mov %esp, %edi # Copy the stack start to edi
    movzx %bl, %bx
    movzx %bx, %ebx # Clear upper ebx, don't need MSR addr anymore
    shl $12, %ebx # Make size full byte count (* 4K)
    add %ebx, %esp # Set the Stack Pointer as full linear address
    sub $4, %esp

    # review:
    # esi[31:24]=Flags; esi[15,8]= Node#; esi[7,0]= core# (relative to node)
    # edi - 32b start address of stack block
    # ebx - size of stack block
    # esp - 32b linear stack pointer


    # Determine mode for SS base;
    mov %cr0, %ecx # Check for 32-bit protect mode
    bt $CR0_PE, %ecx #
    #.if (!carry?) # PE=0 means real mode
    jc Protected32Mode
    mov %cs, %cx # PE=1
    cmp $0x0D000, %cx # Check for CS
    jb Protected32Mode # If CS < D000, it is a selector instead of a segment
            # alter SS:ESP for 16b Real Mode:
Real16bMode:
    mov %edi, %eax
    shr $4, %eax # Create a Real Mode segment for ss, ds, es
    mov %ax, %ss
    mov %ax, %ds
    mov %ax, %es
    shl $4, %eax
    sub %eax, %edi # Adjust the clearing pointer for Seg:Offset mode
    mov %ebx, %esp # Make SP an offset from SS
    sub $4, %esp #
    # .endif # endif
    # #else
    # Default is to use Protected 32b Mode
    #.endif
    ;
Protected32Mode:

    # Clear The Stack
    # Now that we have set the location and the MTRRs, initialize the cache by
    # reading then writing to zero all of the stack area.
    # review:
    # ss - Stack base
    # esp - stack pointer
    # ebx - size of stack block
    # esi[31:24]=Flags; esi[15,8]= Node#; esi[7,0]= core# (relative to node)
    # edi - address of start of stack block


ClearTheStack: # Stack base is in SS, stack pointer is in ESP
    shr $2, %ebx # ebx = stack block size in dwords
    mov %bx, %cx #
    # Check our flags - Don't clear an existing stack
    #.if ( !(esi & 0FF000000h)) # Check our flags
    test $(1 << FLAG_STACK_REENTRY), %esi
    jne 1f
        cld
        mov %edi, %esi
        rep lodsl (%esi) # Pre-load the range
        xor %eax, %eax
        mov %bx, %cx
        mov %edi, %esi # Preserve base for push on stack
        rep stosl (%edi) # Clear the range
        movl $0x0ABCDDCBA, (%esp) # Put marker in top stack dword
        shl $2, %ebx # Put stack size and base
        push %ebx # in top of stack
        push %esi

        mov %ebx, %ecx # Return size of stack in bytes
        xor %eax, %eax # eax = 0 : no error return code
        jmp 0f
    #.else
    1:
        movzx %cx, %ecx
        shl $2, %ecx # Return size of stack in bytes
        mov %esi, %eax
        shr $24, %eax # Keep the flags as part of the error report
        or $0x40000000, %eax # eax = AGESA_WARNING (Stack has already been set up)
    #.endif
    0:

    movd %mm0, %ebx # Restore return address
    movd %mm1, %ebp
.endm
# 1573 "src/vendorcode/amd/agesa/gcccar.inc"
.macro AMD_DISABLE_STACK

    mov %ebx, %esp # Save return address

    # get node/core/flags of current executing core
    GET_NODE_ID_CORE_ID # Sets ESI[15,8]= Node#; ESI[7,0]= core# (relative to node)

    # Turn on modification enable bit
    mov $MTRR_SYS_CFG, %ecx # MSR:C001_0010
    _RDMSR
    bts $MTRR_FIX_DRAM_MOD_EN, %eax # Enable modifications
    _WRMSR

    # Set lower 640K MTRRs for Write-Back memory caching
    mov $AMD_MTRR_FIX64k_00000, %ecx
    mov $0x1E1E1E1E, %eax
    mov %eax, %edx
    _WRMSR # 0 - 512K = WB Mem
    mov $AMD_MTRR_FIX16k_80000, %ecx
    _WRMSR # 512K - 640K = WB Mem

    # Turn off modification enable bit
    mov $MTRR_SYS_CFG, %ecx # MSR:C001_0010
    _RDMSR
    btr $MTRR_FIX_DRAM_MOD_EN, %eax # Disable modification
    _WRMSR

    AMD_DISABLE_STACK_FAMILY_HOOK # Re-Enable 'normal' cache operations

    mov %esp, %ebx
    xor %eax, %eax

.endm
# 31 "./src/cpu/amd/agesa_wrapper/family14/cache_as_ram.inc" 2







.code32
.globl cache_as_ram_setup, disable_cache_as_ram, cache_as_ram_setup_out

cache_as_ram_setup:

  movb $0xa0, %al; outb %al, $0x80




  movl %cr4, %eax
  orl $(3<<9), %eax
  movl %eax, %cr4


  mov $1, %eax
  cpuid
  shr $24, %ebx


  cvtsi2sd %ebp, %xmm0




  cvtsi2sd %ebx, %xmm1

  movb $0xa1, %al; outb %al, $0x80
  AMD_ENABLE_STACK

  movb $0xa1, %al; outb %al, $0x80


  cvtsd2si %xmm0, %edx


  cvtsd2si %xmm1, %ebx

  pushl %ebx
  pushl %edx
  call cache_as_ram_main


  movb $0xaf, %al; outb %al, $0x80
stop:
  jmp stop

disable_cache_as_ram:

  cvtsi2sd %esp, %xmm0

  AMD_DISABLE_STACK


  cvtsd2si %xmm0, %esp

  ret

cache_as_ram_setup_out:
# 6 "build/romstage/crt0.S" 2
# 1 "build/mainboard/amd/persimmon/romstage.inc" 1
 .file "romstage.c"
 .section .debug_abbrev,"",@progbits
.Ldebug_abbrev0:
 .section .debug_info,"",@progbits
.Ldebug_info0:
 .section .debug_line,"",@progbits
.Ldebug_line0:
 .section .rom.text
.Ltext0:
 .cfi_sections .debug_frame
 .type boot_cpu, @function
boot_cpu:
.LFB150:
 .file 1 "src/cpu/x86/lapic/boot_cpu.c"
 .loc 1 4 0
 .cfi_startproc
.LVL0:
.LBB212:
.LBB213:
 .file 2 "src/include/cpu/x86/msr.h"
 .loc 2 45 0
 movl $27, %ecx
/APP
/ 45 "src/include/cpu/x86/msr.h" 1
 rdmsr
/ 0 "" 2
.LVL1:
/NO_APP
.LBE213:
.LBE212:
 .loc 1 8 0
 testb $1, %ah
 setne %al
.LVL2:
 movzbl %al, %eax
 .loc 1 10 0
 ret
 .cfi_endproc
.LFE150:
 .size boot_cpu, .-boot_cpu
.globl setup_i8254
 .type setup_i8254, @function
setup_i8254:
.LFB151:
 .file 3 "src/pc80/i8254.c"
 .loc 3 27 0
 .cfi_startproc
.LVL3:
.LBB214:
.LBB215:
 .file 4 "src/arch/x86/include/arch/io.h"
 .loc 4 46 0
 movb $54, %al
/APP
/ 46 "src/arch/x86/include/arch/io.h" 1
 outb %al, $67
/ 0 "" 2
.LVL4:
/NO_APP
.LBE215:
.LBE214:
.LBB216:
.LBB217:
 xorl %eax, %eax
/APP
/ 46 "src/arch/x86/include/arch/io.h" 1
 outb %al, $64
/ 0 "" 2
.LVL5:
/NO_APP
.LBE217:
.LBE216:
.LBB218:
.LBB219:
/APP
/ 46 "src/arch/x86/include/arch/io.h" 1
 outb %al, $64
/ 0 "" 2
.LVL6:
/NO_APP
.LBE219:
.LBE218:
.LBB220:
.LBB221:
 movb $86, %al
/APP
/ 46 "src/arch/x86/include/arch/io.h" 1
 outb %al, $67
/ 0 "" 2
.LVL7:
/NO_APP
.LBE221:
.LBE220:
.LBB222:
.LBB223:
 movb $18, %al
/APP
/ 46 "src/arch/x86/include/arch/io.h" 1
 outb %al, $65
/ 0 "" 2
/NO_APP
.LBE223:
.LBE222:
 .loc 3 36 0
 ret
 .cfi_endproc
.LFE151:
 .size setup_i8254, .-setup_i8254
.globl setup_i8259
 .type setup_i8259, @function
setup_i8259:
.LFB152:
 .file 5 "src/pc80/i8259.c"
 .loc 5 60 0
 .cfi_startproc
.LVL8:
.LBB224:
.LBB225:
 .loc 4 46 0
 movb $17, %al
/APP
/ 46 "src/arch/x86/include/arch/io.h" 1
 outb %al, $32
/ 0 "" 2
.LVL9:
/NO_APP
.LBE225:
.LBE224:
.LBB226:
.LBB227:
/APP
/ 46 "src/arch/x86/include/arch/io.h" 1
 outb %al, $160
/ 0 "" 2
.LVL10:
/NO_APP
.LBE227:
.LBE226:
.LBB228:
.LBB229:
 movb $32, %al
/APP
/ 46 "src/arch/x86/include/arch/io.h" 1
 outb %al, $33
/ 0 "" 2
.LVL11:
/NO_APP
.LBE229:
.LBE228:
.LBB230:
.LBB231:
 movb $40, %al
/APP
/ 46 "src/arch/x86/include/arch/io.h" 1
 outb %al, $161
/ 0 "" 2
.LVL12:
/NO_APP
.LBE231:
.LBE230:
.LBB232:
.LBB233:
 movb $4, %al
/APP
/ 46 "src/arch/x86/include/arch/io.h" 1
 outb %al, $33
/ 0 "" 2
.LVL13:
/NO_APP
.LBE233:
.LBE232:
.LBB234:
.LBB235:
 movb $2, %al
/APP
/ 46 "src/arch/x86/include/arch/io.h" 1
 outb %al, $161
/ 0 "" 2
.LVL14:
/NO_APP
.LBE235:
.LBE234:
.LBB236:
.LBB237:
 movb $1, %al
/APP
/ 46 "src/arch/x86/include/arch/io.h" 1
 outb %al, $33
/ 0 "" 2
.LVL15:
/NO_APP
.LBE237:
.LBE236:
.LBB238:
.LBB239:
/APP
/ 46 "src/arch/x86/include/arch/io.h" 1
 outb %al, $161
/ 0 "" 2
.LVL16:
/NO_APP
.LBE239:
.LBE238:
.LBB240:
.LBB241:
 movb $-1, %al
/APP
/ 46 "src/arch/x86/include/arch/io.h" 1
 outb %al, $161
/ 0 "" 2
.LVL17:
/NO_APP
.LBE241:
.LBE240:
.LBB242:
.LBB243:
 movb $-5, %al
/APP
/ 46 "src/arch/x86/include/arch/io.h" 1
 outb %al, $33
/ 0 "" 2
/NO_APP
.LBE243:
.LBE242:
 .loc 5 101 0
 ret
 .cfi_endproc
.LFE152:
 .size setup_i8259, .-setup_i8259
 .section .rom.data.str1.1,"aMS",@progbits,1
.LC0:
 .string "%s: current interrupts are 0x%x\n"
.LC1:
 .string "%s: try to set interrupts 0x%x\n"
 .section .rom.text
.globl i8259_configure_irq_trigger
 .type i8259_configure_irq_trigger, @function
i8259_configure_irq_trigger:
.LFB153:
 .loc 5 113 0
 .cfi_startproc
.LVL18:
 pushl %esi
.LCFI0:
 .cfi_def_cfa_offset 8
.LBB244:
.LBB245:
 .loc 4 62 0
 movl $1232, %edx
.LBE245:
.LBE244:
 .loc 5 113 0
 pushl %ebx
.LCFI1:
 .cfi_def_cfa_offset 12
 subl $20, %esp
.LCFI2:
 .cfi_def_cfa_offset 32
 .loc 5 113 0
 movl 32(%esp), %ecx
.LBB247:
.LBB246:
 .loc 4 62 0
/APP
/ 62 "src/arch/x86/include/arch/io.h" 1
 inb %dx, %al
/ 0 "" 2
/NO_APP
 movl %eax, %esi
 .cfi_offset 3, -12
 .cfi_offset 6, -8
.LVL19:
.LBE246:
.LBE247:
.LBB248:
.LBB249:
 movb $-47, %dl
/APP
/ 62 "src/arch/x86/include/arch/io.h" 1
 inb %dx, %al
/ 0 "" 2
.LVL20:
/NO_APP
.LBE249:
.LBE248:
 .loc 5 114 0
 movl %eax, %ebx
 andw $255, %si
.LVL21:
 sall $8, %ebx
 orl %esi, %ebx
.LVL22:
 .loc 5 116 0
 movzwl %bx, %eax
.LVL23:
 pushl %eax
.LCFI3:
 .cfi_def_cfa_offset 36
 pushl $__func__.3515
.LCFI4:
 .cfi_def_cfa_offset 40
 pushl $.LC0
.LCFI5:
 .cfi_def_cfa_offset 44
 pushl $8
.LCFI6:
 .cfi_def_cfa_offset 48
 movl %ecx, 28(%esp)
 .cfi_escape 0x2e,0x10
 call do_printk
 .loc 5 117 0
 addl $16, %esp
.LCFI7:
 .cfi_def_cfa_offset 32
 cmpl $0, 36(%esp)
 movl 12(%esp), %ecx
 je .L5
 .loc 5 118 0
 movl $1, %eax
 sall %cl, %eax
 orl %eax, %ebx
.LVL24:
 jmp .L6
.L5:
 .loc 5 120 0
 movl $-2, %eax
 roll %cl, %eax
 andl %eax, %ebx
.LVL25:
.L6:
 .loc 5 123 0 discriminator 1
 movzwl %bx, %eax
 pushl %eax
.LCFI8:
 .cfi_def_cfa_offset 36
 pushl $__func__.3515
.LCFI9:
 .cfi_def_cfa_offset 40
 pushl $.LC1
.LCFI10:
 .cfi_def_cfa_offset 44
 pushl $8
.LCFI11:
 .cfi_def_cfa_offset 48
 call do_printk
.LVL26:
.LBB250:
.LBB251:
 .loc 4 46 0 discriminator 1
 movl $1232, %edx
 movb %bl, %al
/APP
/ 46 "src/arch/x86/include/arch/io.h" 1
 outb %al, %dx
/ 0 "" 2
.LVL27:
/NO_APP
.LBE251:
.LBE250:
 .loc 5 125 0 discriminator 1
 shrw $8, %bx
.LVL28:
.LBB252:
.LBB253:
 .loc 4 46 0 discriminator 1
 movb $-47, %dl
 movb %bl, %al
/APP
/ 46 "src/arch/x86/include/arch/io.h" 1
 outb %al, %dx
/ 0 "" 2
/NO_APP
.LBE253:
.LBE252:
 .loc 5 139 0 discriminator 1
 addl $36, %esp
.LCFI12:
 .cfi_def_cfa_offset 28
 popl %ebx
 .cfi_restore 3
.LCFI13:
 .cfi_def_cfa_offset 24
 popl %esi
 .cfi_restore 6
.LCFI14:
 .cfi_def_cfa_offset 20
 ret
.LCFI15:
 .cfi_def_cfa_offset 4
 .cfi_endproc
.LFE153:
 .size i8259_configure_irq_trigger, .-i8259_configure_irq_trigger
 .section .rom.data.str1.1
.LC2:
 .string "BIST failed: %08x"
.LC3:
 .string "\n"
.LC4:
 .string "BSP Family_Model: %08x \n"
.LC5:
 .string "cpu_init_detectedx = %08lx \n"
.LC6:
 .string "agesawrapper_amdinitreset failed: %x \n"
.LC7:
 .string "Got past sb800_early_setup\n"
.LC8:
 .string "agesawrapper_amdinitearly failed: %x \n"
.LC9:
 .string "Got past agesawrapper_amdinitearly\n"
.LC10:
 .string "agesawrapper_amdinitpost failed: %x \n"
.LC11:
 .string "Got past agesawrapper_amdinitpost\n"
.LC12:
 .string "agesawrapper_amdinitenv failed: %x \n"
.LC13:
 .string "Got past agesawrapper_amdinitenv\n"
 .section .rom.text
.globl cache_as_ram_main
 .type cache_as_ram_main, @function
cache_as_ram_main:
.LFB154:
 .file 6 "src/mainboard/amd/persimmon/romstage.c"
 .loc 6 46 0
 .cfi_startproc
.LVL29:
 pushl %esi
.LCFI16:
 .cfi_def_cfa_offset 8
.LBB254:
.LBB255:
 .file 7 "src/vendorcode/amd/agesa/Include/gcc-intrin.h"
 .loc 7 462 0
 movl $-4194299, %eax
 xorl %edx, %edx
 movl $524, %ecx
.LBE255:
.LBE254:
 .loc 6 46 0
 pushl %ebx
.LCFI17:
 .cfi_def_cfa_offset 12
 subl $4, %esp
.LCFI18:
 .cfi_def_cfa_offset 16
 .loc 6 46 0
 movl 16(%esp), %ebx
 .cfi_offset 3, -12
 .cfi_offset 6, -8
 movl 20(%esp), %esi
.LBB257:
.LBB256:
 .loc 7 462 0
/APP
/ 462 "src/vendorcode/amd/agesa/Include/gcc-intrin.h" 1
 wrmsr

/ 0 "" 2
.LVL30:
/NO_APP
.LBE256:
.LBE257:
.LBB258:
.LBB259:
 movl $-4192256, %eax
 movl $15, %edx
 movb $13, %cl
/APP
/ 462 "src/vendorcode/amd/agesa/Include/gcc-intrin.h" 1
 wrmsr

/ 0 "" 2
.LVL31:
/NO_APP
.LBE259:
.LBE258:
.LBB260:
.LBB261:
 xorl %eax, %eax
 xorl %edx, %edx
 movl $-1073676190, %ecx
/APP
/ 462 "src/vendorcode/amd/agesa/Include/gcc-intrin.h" 1
 wrmsr

/ 0 "" 2
/NO_APP
.LBE261:
.LBE260:
 .loc 6 58 0
 call boot_cpu
 testl %eax, %eax
 je .L8
.LVL32:
.LBB262:
.LBB263:
.LBB264:
 .loc 4 46 0
 movl $3286, %edx
 movb $36, %al
/APP
/ 46 "src/arch/x86/include/arch/io.h" 1
 outb %al, %dx
/ 0 "" 2
.LVL33:
/NO_APP
.LBE264:
.LBE263:
.LBB265:
.LBB266:
 .loc 4 62 0
 movb $-41, %dl
/APP
/ 62 "src/arch/x86/include/arch/io.h" 1
 inb %dx, %al
/ 0 "" 2
.LVL34:
/NO_APP
.LBE266:
.LBE265:
 .loc 6 64 0
 orl $1, %eax
.LVL35:
 .loc 6 65 0
 andl $-3, %eax
.LVL36:
.LBB267:
.LBB268:
 .loc 4 46 0
/APP
/ 46 "src/arch/x86/include/arch/io.h" 1
 outb %al, %dx
/ 0 "" 2
/NO_APP
.LBE268:
.LBE267:
 .loc 6 69 0
 movl -19395008, %eax
 andl $-6, %eax
 movl %eax, -19395008
 .loc 6 70 0
 movl -19395008, %eax
 orl $2, %eax
 movl %eax, -19395008
.LVL37:
.L8:
.LBE262:
 .loc 6 74 0
 call boot_cpu
 testl %eax, %eax
 je .L9
.LVL38:
.LBB269:
.LBB270:
 .loc 7 91 0
 movl $3320, %edx
 movl $-2147441736, %eax
/APP
/ 91 "src/vendorcode/amd/agesa/Include/gcc-intrin.h" 1
 out %eax, %dx
/ 0 "" 2
.LVL39:
/NO_APP
.LBE270:
.LBE269:
.LBB271:
.LBB272:
 .loc 7 62 0
 movb $-4, %dl
/APP
/ 62 "src/vendorcode/amd/agesa/Include/gcc-intrin.h" 1
 in %dx, %eax
/ 0 "" 2
.LVL40:
/NO_APP
.LBE272:
.LBE271:
 .loc 6 77 0
 orl $16777216, %eax
.LVL41:
.LBB273:
.LBB274:
 .loc 7 91 0
/APP
/ 91 "src/vendorcode/amd/agesa/Include/gcc-intrin.h" 1
 out %eax, %dx
/ 0 "" 2
.LVL42:
/NO_APP
.L9:
.LBE274:
.LBE273:
 .loc 6 81 0
 call boot_cpu
 testl %eax, %eax
 je .L10
.LVL43:
.LBB275:
.LBB276:
.LBB277:
 .loc 7 91 0
 movl $3320, %edx
 movl $-2147441760, %eax
/APP
/ 91 "src/vendorcode/amd/agesa/Include/gcc-intrin.h" 1
 out %eax, %dx
/ 0 "" 2
.LVL44:
/NO_APP
.LBE277:
.LBE276:
.LBB278:
.LBB279:
 .loc 7 62 0
 movb $-4, %dl
/APP
/ 62 "src/vendorcode/amd/agesa/Include/gcc-intrin.h" 1
 in %dx, %eax
/ 0 "" 2
/NO_APP
 movl %eax, %ecx
.LVL45:
.LBE279:
.LBE278:
.LBB280:
.LBB281:
 .loc 7 91 0
 movl $-1610612734, %eax
/APP
/ 91 "src/vendorcode/amd/agesa/Include/gcc-intrin.h" 1
 out %eax, %dx
/ 0 "" 2
/NO_APP
.LBE281:
.LBE280:
 .loc 6 88 0
 movl -1610612724, %eax
 andb $63, %ah
 orb $64, %ah
 movl %eax, -1610612724
 .loc 6 89 0
 movl -1610612736, %eax
 orl $262144, %eax
 movl %eax, -1610612736
.LVL46:
.LBB282:
.LBB283:
 .loc 7 91 0
 movl %ecx, %eax
/APP
/ 91 "src/vendorcode/amd/agesa/Include/gcc-intrin.h" 1
 out %eax, %dx
/ 0 "" 2
.LVL47:
/NO_APP
.L10:
.LBE283:
.LBE282:
.LBE275:
 .loc 6 93 0
 testl %esi, %esi
 jne .L11
 .loc 6 93 0 is_stmt 0 discriminator 1
 call boot_cpu
 testl %eax, %eax
 je .L11
 .loc 6 94 0 is_stmt 1
 subl $12, %esp
.LCFI19:
 .cfi_def_cfa_offset 28
 pushl $48
.LCFI20:
 .cfi_def_cfa_offset 32
 .cfi_escape 0x2e,0x10
 call post_code
 .loc 6 95 0
 call sb_poweron_init
 .loc 6 97 0
 movl $49, (%esp)
 call post_code
.LVL48:
.LBB284:
.LBB285:
.LBB286:
.LBB287:
.LBB288:
 .loc 4 46 0
 movb $-121, %al
/APP
/ 46 "src/arch/x86/include/arch/io.h" 1
 outb %al, $78
/ 0 "" 2
.LVL49:
/NO_APP
.LBE288:
.LBE287:
.LBB289:
.LBB290:
/APP
/ 46 "src/arch/x86/include/arch/io.h" 1
 outb %al, $78
/ 0 "" 2
.LVL50:
/NO_APP
.LBE290:
.LBE289:
.LBE286:
.LBE285:
.LBB291:
.LBB292:
.LBB293:
.LBB294:
.LBB295:
.LBB296:
 movb $7, %al
/APP
/ 46 "src/arch/x86/include/arch/io.h" 1
 outb %al, $78
/ 0 "" 2
.LVL51:
/NO_APP
.LBE296:
.LBE295:
.LBB297:
.LBB298:
 movb $16, %al
/APP
/ 46 "src/arch/x86/include/arch/io.h" 1
 outb %al, $79
/ 0 "" 2
.LVL52:
/NO_APP
.LBE298:
.LBE297:
.LBE294:
.LBE293:
.LBE292:
.LBE291:
.LBB299:
.LBB300:
.LBB301:
.LBB302:
.LBB303:
 movb $48, %dl
 movb %dl, %al
/APP
/ 46 "src/arch/x86/include/arch/io.h" 1
 outb %al, $78
/ 0 "" 2
.LVL53:
/NO_APP
.LBE303:
.LBE302:
.LBB304:
.LBB305:
 xorl %eax, %eax
/APP
/ 46 "src/arch/x86/include/arch/io.h" 1
 outb %al, $79
/ 0 "" 2
.LVL54:
/NO_APP
.LBE305:
.LBE304:
.LBE301:
.LBE300:
.LBE299:
.LBB306:
.LBB307:
.LBB308:
.LBB309:
.LBB310:
 movb $96, %al
/APP
/ 46 "src/arch/x86/include/arch/io.h" 1
 outb %al, $78
/ 0 "" 2
.LVL55:
/NO_APP
.LBE310:
.LBE309:
.LBB311:
.LBB312:
 movb $3, %al
/APP
/ 46 "src/arch/x86/include/arch/io.h" 1
 outb %al, $79
/ 0 "" 2
.LVL56:
/NO_APP
.LBE312:
.LBE311:
.LBE308:
.LBE307:
.LBB313:
.LBB314:
.LBB315:
.LBB316:
 movb $97, %al
/APP
/ 46 "src/arch/x86/include/arch/io.h" 1
 outb %al, $78
/ 0 "" 2
.LVL57:
/NO_APP
.LBE316:
.LBE315:
.LBB317:
.LBB318:
 movb $-8, %al
/APP
/ 46 "src/arch/x86/include/arch/io.h" 1
 outb %al, $79
/ 0 "" 2
.LVL58:
/NO_APP
.LBE318:
.LBE317:
.LBE314:
.LBE313:
.LBE306:
.LBB319:
.LBB320:
.LBB321:
.LBB322:
.LBB323:
 movb %dl, %al
/APP
/ 46 "src/arch/x86/include/arch/io.h" 1
 outb %al, $78
/ 0 "" 2
.LVL59:
/NO_APP
.LBE323:
.LBE322:
.LBB324:
.LBB325:
 movb $1, %al
/APP
/ 46 "src/arch/x86/include/arch/io.h" 1
 outb %al, $79
/ 0 "" 2
.LVL60:
/NO_APP
.LBE325:
.LBE324:
.LBE321:
.LBE320:
.LBE319:
.LBB326:
.LBB327:
.LBB328:
.LBB329:
 movb $-86, %al
/APP
/ 46 "src/arch/x86/include/arch/io.h" 1
 outb %al, $78
/ 0 "" 2
/NO_APP
.LBE329:
.LBE328:
.LBE327:
.LBE326:
.LBE284:
 .loc 6 99 0
 call console_init
 addl $16, %esp
.LCFI21:
 .cfi_def_cfa_offset 16
.LVL61:
.L11:
 .loc 6 103 0
 subl $12, %esp
.LCFI22:
 .cfi_def_cfa_offset 28
 pushl $52
.LCFI23:
 .cfi_def_cfa_offset 32
 call post_code
.LVL62:
.LBB330:
.LBB331:
 .file 8 "src/include/cpu/x86/bist.h"
 .loc 8 6 0
 addl $16, %esp
.LCFI24:
 .cfi_def_cfa_offset 16
 testl %ebx, %ebx
 je .L12
 .loc 8 8 0
 pushl %ecx
.LCFI25:
 .cfi_def_cfa_offset 20
 pushl %ebx
.LCFI26:
 .cfi_def_cfa_offset 24
 pushl $.LC2
.LCFI27:
 .cfi_def_cfa_offset 28
 pushl $0
.LCFI28:
 .cfi_def_cfa_offset 32
 call do_printk
 .loc 8 13 0
 movl $.LC3, (%esp)
 call die
.LCFI29:
 .cfi_def_cfa_offset 16
.L12:
.LVL63:
.LBE331:
.LBE330:
.LBB332:
.LBB333:
 .file 9 "src/arch/x86/include/arch/cpu.h"
 .loc 9 55 0
 movl $1, %eax
/APP
/ 55 "src/arch/x86/include/arch/cpu.h" 1
 cpuid
/ 0 "" 2
.LVL64:
/NO_APP
.LBE333:
.LBE332:
 .loc 6 108 0
 pushl %edx
.LCFI30:
 .cfi_def_cfa_offset 20
 pushl %eax
.LCFI31:
 .cfi_def_cfa_offset 24
 pushl $.LC4
.LCFI32:
 .cfi_def_cfa_offset 28
 pushl $7
.LCFI33:
 .cfi_def_cfa_offset 32
 call do_printk
.LVL65:
 .loc 6 109 0
 addl $12, %esp
.LCFI34:
 .cfi_def_cfa_offset 20
 pushl %esi
.LCFI35:
 .cfi_def_cfa_offset 24
 pushl $.LC5
.LCFI36:
 .cfi_def_cfa_offset 28
 pushl $7
.LCFI37:
 .cfi_def_cfa_offset 32
 call do_printk
 .loc 6 111 0
 movl $53, (%esp)
 call post_code
 .loc 6 112 0
 call agesawrapper_amdinitmmio
 .loc 6 114 0
 movl $55, (%esp)
 call post_code
 .loc 6 115 0
 call agesawrapper_amdinitreset
.LVL66:
 .loc 6 116 0
 addl $16, %esp
.LCFI38:
 .cfi_def_cfa_offset 16
 testl %eax, %eax
 je .L13
 .loc 6 117 0 discriminator 1
 pushl %esi
.LCFI39:
 .cfi_def_cfa_offset 20
 pushl %eax
.LCFI40:
 .cfi_def_cfa_offset 24
 pushl $.LC6
.LCFI41:
 .cfi_def_cfa_offset 28
 pushl $7
.LCFI42:
 .cfi_def_cfa_offset 32
 call do_printk
.LVL67:
 addl $16, %esp
.LCFI43:
 .cfi_def_cfa_offset 16
.L13:
 .loc 6 120 0
 subl $12, %esp
.LCFI44:
 .cfi_def_cfa_offset 28
 pushl $56
.LCFI45:
 .cfi_def_cfa_offset 32
 call post_code
 .loc 6 121 0
 popl %ecx
.LCFI46:
 .cfi_def_cfa_offset 28
 popl %ebx
.LCFI47:
 .cfi_def_cfa_offset 24
 pushl $.LC7
.LCFI48:
 .cfi_def_cfa_offset 28
 pushl $7
.LCFI49:
 .cfi_def_cfa_offset 32
 call do_printk
 .loc 6 123 0
 movl $57, (%esp)
 call post_code
 .loc 6 124 0
 call agesawrapper_amdinitearly
.LVL68:
 .loc 6 125 0
 addl $16, %esp
.LCFI50:
 .cfi_def_cfa_offset 16
 testl %eax, %eax
 je .L14
 .loc 6 126 0 discriminator 1
 pushl %edx
.LCFI51:
 .cfi_def_cfa_offset 20
 pushl %eax
.LCFI52:
 .cfi_def_cfa_offset 24
 pushl $.LC8
.LCFI53:
 .cfi_def_cfa_offset 28
 pushl $7
.LCFI54:
 .cfi_def_cfa_offset 32
 call do_printk
.LVL69:
 addl $16, %esp
.LCFI55:
 .cfi_def_cfa_offset 16
.L14:
 .loc 6 128 0 discriminator 1
 pushl %esi
.LCFI56:
 .cfi_def_cfa_offset 20
 pushl %esi
.LCFI57:
 .cfi_def_cfa_offset 24
 pushl $.LC9
.LCFI58:
 .cfi_def_cfa_offset 28
 pushl $7
.LCFI59:
 .cfi_def_cfa_offset 32
 call do_printk
 .loc 6 130 0 discriminator 1
 movl $64, (%esp)
 call post_code
 .loc 6 131 0 discriminator 1
 call agesawrapper_amdinitpost
.LVL70:
 .loc 6 132 0 discriminator 1
 addl $16, %esp
.LCFI60:
 .cfi_def_cfa_offset 16
 testl %eax, %eax
 je .L15
 .loc 6 133 0 discriminator 1
 pushl %ebx
.LCFI61:
 .cfi_def_cfa_offset 20
 pushl %eax
.LCFI62:
 .cfi_def_cfa_offset 24
 pushl $.LC10
.LCFI63:
 .cfi_def_cfa_offset 28
 pushl $7
.LCFI64:
 .cfi_def_cfa_offset 32
 call do_printk
.LVL71:
 addl $16, %esp
.LCFI65:
 .cfi_def_cfa_offset 16
.L15:
 .loc 6 135 0 discriminator 1
 pushl %ecx
.LCFI66:
 .cfi_def_cfa_offset 20
 pushl %ecx
.LCFI67:
 .cfi_def_cfa_offset 24
 pushl $.LC11
.LCFI68:
 .cfi_def_cfa_offset 28
 pushl $7
.LCFI69:
 .cfi_def_cfa_offset 32
 call do_printk
 .loc 6 137 0 discriminator 1
 movl $65, (%esp)
 call post_code
 .loc 6 138 0 discriminator 1
 call agesawrapper_amdinitenv
.LVL72:
 .loc 6 139 0 discriminator 1
 addl $16, %esp
.LCFI70:
 .cfi_def_cfa_offset 16
 testl %eax, %eax
 je .L16
 .loc 6 140 0 discriminator 1
 pushl %edx
.LCFI71:
 .cfi_def_cfa_offset 20
 pushl %eax
.LCFI72:
 .cfi_def_cfa_offset 24
 pushl $.LC12
.LCFI73:
 .cfi_def_cfa_offset 28
 pushl $7
.LCFI74:
 .cfi_def_cfa_offset 32
 call do_printk
.LVL73:
 addl $16, %esp
.LCFI75:
 .cfi_def_cfa_offset 16
.L16:
 .loc 6 142 0 discriminator 1
 pushl %eax
.LCFI76:
 .cfi_def_cfa_offset 20
 pushl %eax
.LCFI77:
 .cfi_def_cfa_offset 24
 pushl $.LC13
.LCFI78:
 .cfi_def_cfa_offset 28
 pushl $7
.LCFI79:
 .cfi_def_cfa_offset 32
 call do_printk
 .loc 6 145 0 discriminator 1
 movl $65, (%esp)
 call post_code
 .loc 6 146 0 discriminator 1
 call setup_i8259
 .loc 6 149 0 discriminator 1
 movl $66, (%esp)
 call post_code
 .loc 6 150 0 discriminator 1
 call setup_i8254
 .loc 6 152 0 discriminator 1
 movl $80, (%esp)
 call post_code
 .loc 6 153 0 discriminator 1
 movl $0, (%esp)
 call copy_and_run
 .loc 6 155 0 discriminator 1
 movl $84, 32(%esp)
 .loc 6 156 0 discriminator 1
 addl $20, %esp
.LCFI80:
 .cfi_def_cfa_offset 28
 popl %ebx
 .cfi_restore 3
.LCFI81:
 .cfi_def_cfa_offset 24
 popl %esi
 .cfi_restore 6
.LCFI82:
 .cfi_def_cfa_offset 20
 .loc 6 155 0 discriminator 1
 jmp post_code
.LCFI83:
 .cfi_def_cfa_offset 4
 .cfi_endproc
.LFE154:
 .size cache_as_ram_main, .-cache_as_ram_main
 .section .rom.data
 .align 4
 .type __func__.3515, @object
 .size __func__.3515, 28
__func__.3515:
 .string "i8259_configure_irq_trigger"
 .section .rom.text
.Letext0:
 .section .debug_loc,"",@progbits
.Ldebug_loc0:
.LLST0:
 .long .LVL1-.Ltext0
 .long .LVL2-.Ltext0
 .value 0x9
 .byte 0x70
 .sleb128 0
 .byte 0xa
 .value 0x100
 .byte 0x1a
 .byte 0x30
 .byte 0x2e
 .byte 0x9f
 .long 0x0
 .long 0x0
.LLST1:
 .long .LFB153-.Ltext0
 .long .LCFI0-.Ltext0
 .value 0x2
 .byte 0x74
 .sleb128 4
 .long .LCFI0-.Ltext0
 .long .LCFI1-.Ltext0
 .value 0x2
 .byte 0x74
 .sleb128 8
 .long .LCFI1-.Ltext0
 .long .LCFI2-.Ltext0
 .value 0x2
 .byte 0x74
 .sleb128 12
 .long .LCFI2-.Ltext0
 .long .LCFI3-.Ltext0
 .value 0x2
 .byte 0x74
 .sleb128 32
 .long .LCFI3-.Ltext0
 .long .LCFI4-.Ltext0
 .value 0x2
 .byte 0x74
 .sleb128 36
 .long .LCFI4-.Ltext0
 .long .LCFI5-.Ltext0
 .value 0x2
 .byte 0x74
 .sleb128 40
 .long .LCFI5-.Ltext0
 .long .LCFI6-.Ltext0
 .value 0x2
 .byte 0x74
 .sleb128 44
 .long .LCFI6-.Ltext0
 .long .LCFI7-.Ltext0
 .value 0x2
 .byte 0x74
 .sleb128 48
 .long .LCFI7-.Ltext0
 .long .LCFI8-.Ltext0
 .value 0x2
 .byte 0x74
 .sleb128 32
 .long .LCFI8-.Ltext0
 .long .LCFI9-.Ltext0
 .value 0x2
 .byte 0x74
 .sleb128 36
 .long .LCFI9-.Ltext0
 .long .LCFI10-.Ltext0
 .value 0x2
 .byte 0x74
 .sleb128 40
 .long .LCFI10-.Ltext0
 .long .LCFI11-.Ltext0
 .value 0x2
 .byte 0x74
 .sleb128 44
 .long .LCFI11-.Ltext0
 .long .LCFI12-.Ltext0
 .value 0x2
 .byte 0x74
 .sleb128 48
 .long .LCFI12-.Ltext0
 .long .LCFI13-.Ltext0
 .value 0x2
 .byte 0x74
 .sleb128 28
 .long .LCFI13-.Ltext0
 .long .LCFI14-.Ltext0
 .value 0x2
 .byte 0x74
 .sleb128 24
 .long .LCFI14-.Ltext0
 .long .LCFI15-.Ltext0
 .value 0x2
 .byte 0x74
 .sleb128 20
 .long .LCFI15-.Ltext0
 .long .LFE153-.Ltext0
 .value 0x2
 .byte 0x74
 .sleb128 4
 .long 0x0
 .long 0x0
.LLST2:
 .long .LVL22-.Ltext0
 .long .LVL24-.Ltext0
 .value 0x1
 .byte 0x53
 .long .LVL24-.Ltext0
 .long .LVL25-.Ltext0
 .value 0x1
 .byte 0x53
 .long .LVL25-.Ltext0
 .long .LVL28-.Ltext0
 .value 0x1
 .byte 0x53
 .long 0x0
 .long 0x0
.LLST3:
 .long .LVL19-.Ltext0
 .long .LVL20-.Ltext0
 .value 0x1
 .byte 0x50
 .long .LVL20-.Ltext0
 .long .LVL21-.Ltext0
 .value 0x1
 .byte 0x56
 .long 0x0
 .long 0x0
.LLST4:
 .long .LVL20-.Ltext0
 .long .LVL23-.Ltext0
 .value 0x1
 .byte 0x50
 .long 0x0
 .long 0x0
.LLST5:
 .long .LVL26-.Ltext0
 .long .LVL28-.Ltext0
 .value 0x1
 .byte 0x53
 .long 0x0
 .long 0x0
.LLST6:
 .long .LFB154-.Ltext0
 .long .LCFI16-.Ltext0
 .value 0x2
 .byte 0x74
 .sleb128 4
 .long .LCFI16-.Ltext0
 .long .LCFI17-.Ltext0
 .value 0x2
 .byte 0x74
 .sleb128 8
 .long .LCFI17-.Ltext0
 .long .LCFI18-.Ltext0
 .value 0x2
 .byte 0x74
 .sleb128 12
 .long .LCFI18-.Ltext0
 .long .LCFI19-.Ltext0
 .value 0x2
 .byte 0x74
 .sleb128 16
 .long .LCFI19-.Ltext0
 .long .LCFI20-.Ltext0
 .value 0x2
 .byte 0x74
 .sleb128 28
 .long .LCFI20-.Ltext0
 .long .LCFI21-.Ltext0
 .value 0x2
 .byte 0x74
 .sleb128 32
 .long .LCFI21-.Ltext0
 .long .LCFI22-.Ltext0
 .value 0x2
 .byte 0x74
 .sleb128 16
 .long .LCFI22-.Ltext0
 .long .LCFI23-.Ltext0
 .value 0x2
 .byte 0x74
 .sleb128 28
 .long .LCFI23-.Ltext0
 .long .LCFI24-.Ltext0
 .value 0x2
 .byte 0x74
 .sleb128 32
 .long .LCFI24-.Ltext0
 .long .LCFI25-.Ltext0
 .value 0x2
 .byte 0x74
 .sleb128 16
 .long .LCFI25-.Ltext0
 .long .LCFI26-.Ltext0
 .value 0x2
 .byte 0x74
 .sleb128 20
 .long .LCFI26-.Ltext0
 .long .LCFI27-.Ltext0
 .value 0x2
 .byte 0x74
 .sleb128 24
 .long .LCFI27-.Ltext0
 .long .LCFI28-.Ltext0
 .value 0x2
 .byte 0x74
 .sleb128 28
 .long .LCFI28-.Ltext0
 .long .LCFI29-.Ltext0
 .value 0x2
 .byte 0x74
 .sleb128 32
 .long .LCFI29-.Ltext0
 .long .LCFI30-.Ltext0
 .value 0x2
 .byte 0x74
 .sleb128 16
 .long .LCFI30-.Ltext0
 .long .LCFI31-.Ltext0
 .value 0x2
 .byte 0x74
 .sleb128 20
 .long .LCFI31-.Ltext0
 .long .LCFI32-.Ltext0
 .value 0x2
 .byte 0x74
 .sleb128 24
 .long .LCFI32-.Ltext0
 .long .LCFI33-.Ltext0
 .value 0x2
 .byte 0x74
 .sleb128 28
 .long .LCFI33-.Ltext0
 .long .LCFI34-.Ltext0
 .value 0x2
 .byte 0x74
 .sleb128 32
 .long .LCFI34-.Ltext0
 .long .LCFI35-.Ltext0
 .value 0x2
 .byte 0x74
 .sleb128 20
 .long .LCFI35-.Ltext0
 .long .LCFI36-.Ltext0
 .value 0x2
 .byte 0x74
 .sleb128 24
 .long .LCFI36-.Ltext0
 .long .LCFI37-.Ltext0
 .value 0x2
 .byte 0x74
 .sleb128 28
 .long .LCFI37-.Ltext0
 .long .LCFI38-.Ltext0
 .value 0x2
 .byte 0x74
 .sleb128 32
 .long .LCFI38-.Ltext0
 .long .LCFI39-.Ltext0
 .value 0x2
 .byte 0x74
 .sleb128 16
 .long .LCFI39-.Ltext0
 .long .LCFI40-.Ltext0
 .value 0x2
 .byte 0x74
 .sleb128 20
 .long .LCFI40-.Ltext0
 .long .LCFI41-.Ltext0
 .value 0x2
 .byte 0x74
 .sleb128 24
 .long .LCFI41-.Ltext0
 .long .LCFI42-.Ltext0
 .value 0x2
 .byte 0x74
 .sleb128 28
 .long .LCFI42-.Ltext0
 .long .LCFI43-.Ltext0
 .value 0x2
 .byte 0x74
 .sleb128 32
 .long .LCFI43-.Ltext0
 .long .LCFI44-.Ltext0
 .value 0x2
 .byte 0x74
 .sleb128 16
 .long .LCFI44-.Ltext0
 .long .LCFI45-.Ltext0
 .value 0x2
 .byte 0x74
 .sleb128 28
 .long .LCFI45-.Ltext0
 .long .LCFI46-.Ltext0
 .value 0x2
 .byte 0x74
 .sleb128 32
 .long .LCFI46-.Ltext0
 .long .LCFI47-.Ltext0
 .value 0x2
 .byte 0x74
 .sleb128 28
 .long .LCFI47-.Ltext0
 .long .LCFI48-.Ltext0
 .value 0x2
 .byte 0x74
 .sleb128 24
 .long .LCFI48-.Ltext0
 .long .LCFI49-.Ltext0
 .value 0x2
 .byte 0x74
 .sleb128 28
 .long .LCFI49-.Ltext0
 .long .LCFI50-.Ltext0
 .value 0x2
 .byte 0x74
 .sleb128 32
 .long .LCFI50-.Ltext0
 .long .LCFI51-.Ltext0
 .value 0x2
 .byte 0x74
 .sleb128 16
 .long .LCFI51-.Ltext0
 .long .LCFI52-.Ltext0
 .value 0x2
 .byte 0x74
 .sleb128 20
 .long .LCFI52-.Ltext0
 .long .LCFI53-.Ltext0
 .value 0x2
 .byte 0x74
 .sleb128 24
 .long .LCFI53-.Ltext0
 .long .LCFI54-.Ltext0
 .value 0x2
 .byte 0x74
 .sleb128 28
 .long .LCFI54-.Ltext0
 .long .LCFI55-.Ltext0
 .value 0x2
 .byte 0x74
 .sleb128 32
 .long .LCFI55-.Ltext0
 .long .LCFI56-.Ltext0
 .value 0x2
 .byte 0x74
 .sleb128 16
 .long .LCFI56-.Ltext0
 .long .LCFI57-.Ltext0
 .value 0x2
 .byte 0x74
 .sleb128 20
 .long .LCFI57-.Ltext0
 .long .LCFI58-.Ltext0
 .value 0x2
 .byte 0x74
 .sleb128 24
 .long .LCFI58-.Ltext0
 .long .LCFI59-.Ltext0
 .value 0x2
 .byte 0x74
 .sleb128 28
 .long .LCFI59-.Ltext0
 .long .LCFI60-.Ltext0
 .value 0x2
 .byte 0x74
 .sleb128 32
 .long .LCFI60-.Ltext0
 .long .LCFI61-.Ltext0
 .value 0x2
 .byte 0x74
 .sleb128 16
 .long .LCFI61-.Ltext0
 .long .LCFI62-.Ltext0
 .value 0x2
 .byte 0x74
 .sleb128 20
 .long .LCFI62-.Ltext0
 .long .LCFI63-.Ltext0
 .value 0x2
 .byte 0x74
 .sleb128 24
 .long .LCFI63-.Ltext0
 .long .LCFI64-.Ltext0
 .value 0x2
 .byte 0x74
 .sleb128 28
 .long .LCFI64-.Ltext0
 .long .LCFI65-.Ltext0
 .value 0x2
 .byte 0x74
 .sleb128 32
 .long .LCFI65-.Ltext0
 .long .LCFI66-.Ltext0
 .value 0x2
 .byte 0x74
 .sleb128 16
 .long .LCFI66-.Ltext0
 .long .LCFI67-.Ltext0
 .value 0x2
 .byte 0x74
 .sleb128 20
 .long .LCFI67-.Ltext0
 .long .LCFI68-.Ltext0
 .value 0x2
 .byte 0x74
 .sleb128 24
 .long .LCFI68-.Ltext0
 .long .LCFI69-.Ltext0
 .value 0x2
 .byte 0x74
 .sleb128 28
 .long .LCFI69-.Ltext0
 .long .LCFI70-.Ltext0
 .value 0x2
 .byte 0x74
 .sleb128 32
 .long .LCFI70-.Ltext0
 .long .LCFI71-.Ltext0
 .value 0x2
 .byte 0x74
 .sleb128 16
 .long .LCFI71-.Ltext0
 .long .LCFI72-.Ltext0
 .value 0x2
 .byte 0x74
 .sleb128 20
 .long .LCFI72-.Ltext0
 .long .LCFI73-.Ltext0
 .value 0x2
 .byte 0x74
 .sleb128 24
 .long .LCFI73-.Ltext0
 .long .LCFI74-.Ltext0
 .value 0x2
 .byte 0x74
 .sleb128 28
 .long .LCFI74-.Ltext0
 .long .LCFI75-.Ltext0
 .value 0x2
 .byte 0x74
 .sleb128 32
 .long .LCFI75-.Ltext0
 .long .LCFI76-.Ltext0
 .value 0x2
 .byte 0x74
 .sleb128 16
 .long .LCFI76-.Ltext0
 .long .LCFI77-.Ltext0
 .value 0x2
 .byte 0x74
 .sleb128 20
 .long .LCFI77-.Ltext0
 .long .LCFI78-.Ltext0
 .value 0x2
 .byte 0x74
 .sleb128 24
 .long .LCFI78-.Ltext0
 .long .LCFI79-.Ltext0
 .value 0x2
 .byte 0x74
 .sleb128 28
 .long .LCFI79-.Ltext0
 .long .LCFI80-.Ltext0
 .value 0x2
 .byte 0x74
 .sleb128 32
 .long .LCFI80-.Ltext0
 .long .LCFI81-.Ltext0
 .value 0x2
 .byte 0x74
 .sleb128 28
 .long .LCFI81-.Ltext0
 .long .LCFI82-.Ltext0
 .value 0x2
 .byte 0x74
 .sleb128 24
 .long .LCFI82-.Ltext0
 .long .LCFI83-.Ltext0
 .value 0x2
 .byte 0x74
 .sleb128 20
 .long .LCFI83-.Ltext0
 .long .LFE154-.Ltext0
 .value 0x2
 .byte 0x74
 .sleb128 4
 .long 0x0
 .long 0x0
.LLST7:
 .long .LVL66-.Ltext0
 .long .LVL67-1-.Ltext0
 .value 0x1
 .byte 0x50
 .long .LVL68-.Ltext0
 .long .LVL69-1-.Ltext0
 .value 0x1
 .byte 0x50
 .long .LVL70-.Ltext0
 .long .LVL71-1-.Ltext0
 .value 0x1
 .byte 0x50
 .long .LVL72-.Ltext0
 .long .LVL73-1-.Ltext0
 .value 0x1
 .byte 0x50
 .long 0x0
 .long 0x0
.LLST8:
 .long .LVL35-.Ltext0
 .long .LVL36-.Ltext0
 .value 0x6
 .byte 0x70
 .sleb128 0
 .byte 0x9
 .byte 0xfd
 .byte 0x1a
 .byte 0x9f
 .long 0x0
 .long 0x0
.LLST9:
 .long .LVL32-.Ltext0
 .long .LVL37-.Ltext0
 .value 0x4
 .byte 0xa
 .value 0xcd6
 .byte 0x9f
 .long 0x0
 .long 0x0
.LLST10:
 .long .LVL32-.Ltext0
 .long .LVL37-.Ltext0
 .value 0x3
 .byte 0x8
 .byte 0x24
 .byte 0x9f
 .long 0x0
 .long 0x0
.LLST11:
 .long .LVL33-.Ltext0
 .long .LVL37-.Ltext0
 .value 0x4
 .byte 0xa
 .value 0xcd7
 .byte 0x9f
 .long 0x0
 .long 0x0
.LLST12:
 .long .LVL34-.Ltext0
 .long .LVL35-.Ltext0
 .value 0x1
 .byte 0x50
 .long 0x0
 .long 0x0
.LLST13:
 .long .LVL35-.Ltext0
 .long .LVL37-.Ltext0
 .value 0x4
 .byte 0xa
 .value 0xcd7
 .byte 0x9f
 .long 0x0
 .long 0x0
.LLST14:
 .long .LVL35-.Ltext0
 .long .LVL36-.Ltext0
 .value 0x6
 .byte 0x70
 .sleb128 0
 .byte 0x9
 .byte 0xfd
 .byte 0x1a
 .byte 0x9f
 .long 0x0
 .long 0x0
.LLST15:
 .long .LVL38-.Ltext0
 .long .LVL42-.Ltext0
 .value 0x6
 .byte 0xd
 .long 0x8000a3b8
 .byte 0x9f
 .long 0x0
 .long 0x0
.LLST16:
 .long .LVL38-.Ltext0
 .long .LVL42-.Ltext0
 .value 0x4
 .byte 0xa
 .value 0xcf8
 .byte 0x9f
 .long 0x0
 .long 0x0
.LLST17:
 .long .LVL39-.Ltext0
 .long .LVL42-.Ltext0
 .value 0x4
 .byte 0xa
 .value 0xcfc
 .byte 0x9f
 .long 0x0
 .long 0x0
.LLST18:
 .long .LVL40-.Ltext0
 .long .LVL41-.Ltext0
 .value 0x1
 .byte 0x50
 .long 0x0
 .long 0x0
.LLST19:
 .long .LVL40-.Ltext0
 .long .LVL41-.Ltext0
 .value 0x9
 .byte 0x70
 .sleb128 0
 .byte 0xc
 .long 0x1000000
 .byte 0x21
 .byte 0x9f
 .long .LVL41-.Ltext0
 .long .LVL42-.Ltext0
 .value 0x1
 .byte 0x50
 .long 0x0
 .long 0x0
.LLST20:
 .long .LVL40-.Ltext0
 .long .LVL42-.Ltext0
 .value 0x4
 .byte 0xa
 .value 0xcfc
 .byte 0x9f
 .long 0x0
 .long 0x0
.LLST21:
 .long .LVL43-.Ltext0
 .long .LVL47-.Ltext0
 .value 0x6
 .byte 0xd
 .long 0xa0000000
 .byte 0x9f
 .long 0x0
 .long 0x0
.LLST22:
 .long .LVL43-.Ltext0
 .long .LVL47-.Ltext0
 .value 0x6
 .byte 0xd
 .long 0x8000a3a0
 .byte 0x9f
 .long 0x0
 .long 0x0
.LLST23:
 .long .LVL43-.Ltext0
 .long .LVL47-.Ltext0
 .value 0x4
 .byte 0xa
 .value 0xcf8
 .byte 0x9f
 .long 0x0
 .long 0x0
.LLST24:
 .long .LVL44-.Ltext0
 .long .LVL47-.Ltext0
 .value 0x4
 .byte 0xa
 .value 0xcfc
 .byte 0x9f
 .long 0x0
 .long 0x0
.LLST25:
 .long .LVL45-.Ltext0
 .long .LVL47-.Ltext0
 .value 0x6
 .byte 0xd
 .long 0xa0000002
 .byte 0x9f
 .long 0x0
 .long 0x0
.LLST26:
 .long .LVL45-.Ltext0
 .long .LVL47-.Ltext0
 .value 0x4
 .byte 0xa
 .value 0xcfc
 .byte 0x9f
 .long 0x0
 .long 0x0
.LLST27:
 .long .LVL46-.Ltext0
 .long .LVL47-.Ltext0
 .value 0x4
 .byte 0xa
 .value 0xcfc
 .byte 0x9f
 .long 0x0
 .long 0x0
.LLST28:
 .long .LVL48-.Ltext0
 .long .LVL61-.Ltext0
 .value 0x4
 .byte 0xa
 .value 0x3f8
 .byte 0x9f
 .long 0x0
 .long 0x0
.LLST29:
 .long .LVL48-.Ltext0
 .long .LVL61-.Ltext0
 .value 0x4
 .byte 0xa
 .value 0x4e10
 .byte 0x9f
 .long 0x0
 .long 0x0
.LLST30:
 .long .LVL48-.Ltext0
 .long .LVL61-.Ltext0
 .value 0x4
 .byte 0xa
 .value 0x4e10
 .byte 0x9f
 .long 0x0
 .long 0x0
.LLST31:
 .long .LVL48-.Ltext0
 .long .LVL61-.Ltext0
 .value 0x3
 .byte 0x8
 .byte 0x4e
 .byte 0x9f
 .long 0x0
 .long 0x0
.LLST32:
 .long .LVL48-.Ltext0
 .long .LVL61-.Ltext0
 .value 0x3
 .byte 0x8
 .byte 0x4e
 .byte 0x9f
 .long 0x0
 .long 0x0
.LLST33:
 .long .LVL48-.Ltext0
 .long .LVL61-.Ltext0
 .value 0x3
 .byte 0x9
 .byte 0x87
 .byte 0x9f
 .long 0x0
 .long 0x0
.LLST34:
 .long .LVL49-.Ltext0
 .long .LVL61-.Ltext0
 .value 0x3
 .byte 0x8
 .byte 0x4e
 .byte 0x9f
 .long 0x0
 .long 0x0
.LLST35:
 .long .LVL49-.Ltext0
 .long .LVL61-.Ltext0
 .value 0x3
 .byte 0x9
 .byte 0x87
 .byte 0x9f
 .long 0x0
 .long 0x0
.LLST36:
 .long .LVL50-.Ltext0
 .long .LVL61-.Ltext0
 .value 0x4
 .byte 0xa
 .value 0x4e10
 .byte 0x9f
 .long 0x0
 .long 0x0
.LLST37:
 .long .LVL50-.Ltext0
 .long .LVL61-.Ltext0
 .value 0x2
 .byte 0x40
 .byte 0x9f
 .long 0x0
 .long 0x0
.LLST38:
 .long .LVL50-.Ltext0
 .long .LVL61-.Ltext0
 .value 0x2
 .byte 0x40
 .byte 0x9f
 .long 0x0
 .long 0x0
.LLST39:
 .long .LVL50-.Ltext0
 .long .LVL61-.Ltext0
 .value 0x2
 .byte 0x37
 .byte 0x9f
 .long 0x0
 .long 0x0
.LLST40:
 .long .LVL50-.Ltext0
 .long .LVL61-.Ltext0
 .value 0x4
 .byte 0xa
 .value 0x4e10
 .byte 0x9f
 .long 0x0
 .long 0x0
.LLST41:
 .long .LVL50-.Ltext0
 .long .LVL61-.Ltext0
 .value 0x3
 .byte 0x8
 .byte 0x4e
 .byte 0x9f
 .long 0x0
 .long 0x0
.LLST42:
 .long .LVL50-.Ltext0
 .long .LVL61-.Ltext0
 .value 0x3
 .byte 0x8
 .byte 0x4e
 .byte 0x9f
 .long 0x0
 .long 0x0
.LLST43:
 .long .LVL50-.Ltext0
 .long .LVL61-.Ltext0
 .value 0x2
 .byte 0x37
 .byte 0x9f
 .long 0x0
 .long 0x0
.LLST44:
 .long .LVL51-.Ltext0
 .long .LVL61-.Ltext0
 .value 0x3
 .byte 0x8
 .byte 0x4f
 .byte 0x9f
 .long 0x0
 .long 0x0
.LLST45:
 .long .LVL51-.Ltext0
 .long .LVL61-.Ltext0
 .value 0x2
 .byte 0x40
 .byte 0x9f
 .long 0x0
 .long 0x0
.LLST46:
 .long .LVL52-.Ltext0
 .long .LVL61-.Ltext0
 .value 0x2
 .byte 0x30
 .byte 0x9f
 .long 0x0
 .long 0x0
.LLST47:
 .long .LVL52-.Ltext0
 .long .LVL61-.Ltext0
 .value 0x4
 .byte 0xa
 .value 0x4e10
 .byte 0x9f
 .long 0x0
 .long 0x0
.LLST48:
 .long .LVL52-.Ltext0
 .long .LVL61-.Ltext0
 .value 0x3
 .byte 0x8
 .byte 0x30
 .byte 0x9f
 .long 0x0
 .long 0x0
.LLST49:
 .long .LVL52-.Ltext0
 .long .LVL61-.Ltext0
 .value 0x2
 .byte 0x30
 .byte 0x9f
 .long 0x0
 .long 0x0
.LLST50:
 .long .LVL52-.Ltext0
 .long .LVL61-.Ltext0
 .value 0x4
 .byte 0xa
 .value 0x4e10
 .byte 0x9f
 .long 0x0
 .long 0x0
.LLST51:
 .long .LVL52-.Ltext0
 .long .LVL61-.Ltext0
 .value 0x3
 .byte 0x8
 .byte 0x4e
 .byte 0x9f
 .long 0x0
 .long 0x0
.LLST52:
 .long .LVL52-.Ltext0
 .long .LVL61-.Ltext0
 .value 0x3
 .byte 0x8
 .byte 0x4e
 .byte 0x9f
 .long 0x0
 .long 0x0
.LLST53:
 .long .LVL52-.Ltext0
 .long .LVL61-.Ltext0
 .value 0x3
 .byte 0x8
 .byte 0x30
 .byte 0x9f
 .long 0x0
 .long 0x0
.LLST54:
 .long .LVL53-.Ltext0
 .long .LVL61-.Ltext0
 .value 0x3
 .byte 0x8
 .byte 0x4f
 .byte 0x9f
 .long 0x0
 .long 0x0
.LLST55:
 .long .LVL53-.Ltext0
 .long .LVL61-.Ltext0
 .value 0x2
 .byte 0x30
 .byte 0x9f
 .long 0x0
 .long 0x0
.LLST56:
 .long .LVL54-.Ltext0
 .long .LVL61-.Ltext0
 .value 0x4
 .byte 0xa
 .value 0x3f8
 .byte 0x9f
 .long 0x0
 .long 0x0
.LLST57:
 .long .LVL54-.Ltext0
 .long .LVL61-.Ltext0
 .value 0x3
 .byte 0x8
 .byte 0x60
 .byte 0x9f
 .long 0x0
 .long 0x0
.LLST58:
 .long .LVL54-.Ltext0
 .long .LVL61-.Ltext0
 .value 0x4
 .byte 0xa
 .value 0x4e10
 .byte 0x9f
 .long 0x0
 .long 0x0
.LLST59:
 .long .LVL54-.Ltext0
 .long .LVL61-.Ltext0
 .value 0x2
 .byte 0x33
 .byte 0x9f
 .long 0x0
 .long 0x0
.LLST60:
 .long .LVL54-.Ltext0
 .long .LVL61-.Ltext0
 .value 0x4
 .byte 0xa
 .value 0x4e10
 .byte 0x9f
 .long 0x0
 .long 0x0
.LLST61:
 .long .LVL54-.Ltext0
 .long .LVL61-.Ltext0
 .value 0x3
 .byte 0x8
 .byte 0x60
 .byte 0x9f
 .long 0x0
 .long 0x0
.LLST62:
 .long .LVL54-.Ltext0
 .long .LVL61-.Ltext0
 .value 0x3
 .byte 0x8
 .byte 0x4e
 .byte 0x9f
 .long 0x0
 .long 0x0
.LLST63:
 .long .LVL54-.Ltext0
 .long .LVL61-.Ltext0
 .value 0x3
 .byte 0x8
 .byte 0x4e
 .byte 0x9f
 .long 0x0
 .long 0x0
.LLST64:
 .long .LVL54-.Ltext0
 .long .LVL61-.Ltext0
 .value 0x3
 .byte 0x8
 .byte 0x60
 .byte 0x9f
 .long 0x0
 .long 0x0
.LLST65:
 .long .LVL55-.Ltext0
 .long .LVL61-.Ltext0
 .value 0x3
 .byte 0x8
 .byte 0x4f
 .byte 0x9f
 .long 0x0
 .long 0x0
.LLST66:
 .long .LVL55-.Ltext0
 .long .LVL61-.Ltext0
 .value 0x2
 .byte 0x33
 .byte 0x9f
 .long 0x0
 .long 0x0
.LLST67:
 .long .LVL56-.Ltext0
 .long .LVL61-.Ltext0
 .value 0x3
 .byte 0x9
 .byte 0xf8
 .byte 0x9f
 .long 0x0
 .long 0x0
.LLST68:
 .long .LVL56-.Ltext0
 .long .LVL61-.Ltext0
 .value 0x3
 .byte 0x8
 .byte 0x61
 .byte 0x9f
 .long 0x0
 .long 0x0
.LLST69:
 .long .LVL56-.Ltext0
 .long .LVL61-.Ltext0
 .value 0x4
 .byte 0xa
 .value 0x4e10
 .byte 0x9f
 .long 0x0
 .long 0x0
.LLST70:
 .long .LVL56-.Ltext0
 .long .LVL61-.Ltext0
 .value 0x3
 .byte 0x8
 .byte 0x4e
 .byte 0x9f
 .long 0x0
 .long 0x0
.LLST71:
 .long .LVL56-.Ltext0
 .long .LVL61-.Ltext0
 .value 0x3
 .byte 0x8
 .byte 0x4e
 .byte 0x9f
 .long 0x0
 .long 0x0
.LLST72:
 .long .LVL56-.Ltext0
 .long .LVL61-.Ltext0
 .value 0x3
 .byte 0x8
 .byte 0x61
 .byte 0x9f
 .long 0x0
 .long 0x0
.LLST73:
 .long .LVL57-.Ltext0
 .long .LVL61-.Ltext0
 .value 0x3
 .byte 0x8
 .byte 0x4f
 .byte 0x9f
 .long 0x0
 .long 0x0
.LLST74:
 .long .LVL57-.Ltext0
 .long .LVL61-.Ltext0
 .value 0x3
 .byte 0x9
 .byte 0xf8
 .byte 0x9f
 .long 0x0
 .long 0x0
.LLST75:
 .long .LVL58-.Ltext0
 .long .LVL61-.Ltext0
 .value 0x2
 .byte 0x31
 .byte 0x9f
 .long 0x0
 .long 0x0
.LLST76:
 .long .LVL58-.Ltext0
 .long .LVL61-.Ltext0
 .value 0x4
 .byte 0xa
 .value 0x4e10
 .byte 0x9f
 .long 0x0
 .long 0x0
.LLST77:
 .long .LVL52-.Ltext0
 .long .LVL61-.Ltext0
 .value 0x3
 .byte 0x8
 .byte 0x30
 .byte 0x9f
 .long 0x0
 .long 0x0
.LLST78:
 .long .LVL58-.Ltext0
 .long .LVL61-.Ltext0
 .value 0x2
 .byte 0x31
 .byte 0x9f
 .long 0x0
 .long 0x0
.LLST79:
 .long .LVL58-.Ltext0
 .long .LVL61-.Ltext0
 .value 0x4
 .byte 0xa
 .value 0x4e10
 .byte 0x9f
 .long 0x0
 .long 0x0
.LLST80:
 .long .LVL58-.Ltext0
 .long .LVL61-.Ltext0
 .value 0x3
 .byte 0x8
 .byte 0x4e
 .byte 0x9f
 .long 0x0
 .long 0x0
.LLST81:
 .long .LVL58-.Ltext0
 .long .LVL61-.Ltext0
 .value 0x3
 .byte 0x8
 .byte 0x4e
 .byte 0x9f
 .long 0x0
 .long 0x0
.LLST82:
 .long .LVL58-.Ltext0
 .long .LVL61-.Ltext0
 .value 0x3
 .byte 0x8
 .byte 0x30
 .byte 0x9f
 .long 0x0
 .long 0x0
.LLST83:
 .long .LVL59-.Ltext0
 .long .LVL61-.Ltext0
 .value 0x3
 .byte 0x8
 .byte 0x4f
 .byte 0x9f
 .long 0x0
 .long 0x0
.LLST84:
 .long .LVL59-.Ltext0
 .long .LVL61-.Ltext0
 .value 0x2
 .byte 0x31
 .byte 0x9f
 .long 0x0
 .long 0x0
.LLST85:
 .long .LVL60-.Ltext0
 .long .LVL61-.Ltext0
 .value 0x4
 .byte 0xa
 .value 0x4e10
 .byte 0x9f
 .long 0x0
 .long 0x0
.LLST86:
 .long .LVL60-.Ltext0
 .long .LVL61-.Ltext0
 .value 0x3
 .byte 0x8
 .byte 0x4e
 .byte 0x9f
 .long 0x0
 .long 0x0
.LLST87:
 .long .LVL60-.Ltext0
 .long .LVL61-.Ltext0
 .value 0x3
 .byte 0x8
 .byte 0x4e
 .byte 0x9f
 .long 0x0
 .long 0x0
.LLST88:
 .long .LVL60-.Ltext0
 .long .LVL61-.Ltext0
 .value 0x3
 .byte 0x9
 .byte 0xaa
 .byte 0x9f
 .long 0x0
 .long 0x0
.LLST89:
 .long .LVL64-.Ltext0
 .long .LVL65-1-.Ltext0
 .value 0x1
 .byte 0x50
 .long 0x0
 .long 0x0
 .file 10 "src/arch/x86/include/stdint.h"
 .file 11 "src/arch/x86/include/arch/romcc_io.h"
 .file 12 "src/vendorcode/amd/agesa/Porting.h"
 .file 13 "src/superio/fintek/f81865f/f81865f_early_serial.c"
 .section .debug_info
 .long 0xde8
 .value 0x2
 .long .Ldebug_abbrev0
 .byte 0x4
 .uleb128 0x1
 .long .LASF54
 .byte 0x1
 .long .LASF55
 .long .LASF56
 .long .Ltext0
 .long .Letext0
 .long .Ldebug_line0
 .uleb128 0x2
 .long .LASF2
 .byte 0xa
 .byte 0xb
 .long 0x30
 .uleb128 0x3
 .byte 0x1
 .byte 0x8
 .long .LASF0
 .uleb128 0x3
 .byte 0x1
 .byte 0x6
 .long .LASF1
 .uleb128 0x2
 .long .LASF3
 .byte 0xa
 .byte 0xe
 .long 0x49
 .uleb128 0x3
 .byte 0x2
 .byte 0x7
 .long .LASF4
 .uleb128 0x3
 .byte 0x2
 .byte 0x5
 .long .LASF5
 .uleb128 0x2
 .long .LASF6
 .byte 0xa
 .byte 0x11
 .long 0x62
 .uleb128 0x3
 .byte 0x4
 .byte 0x7
 .long .LASF7
 .uleb128 0x4
 .byte 0x4
 .byte 0x5
 .string "int"
 .uleb128 0x3
 .byte 0x8
 .byte 0x7
 .long .LASF8
 .uleb128 0x3
 .byte 0x8
 .byte 0x5
 .long .LASF9
 .uleb128 0x5
 .string "u8"
 .byte 0xa
 .byte 0x44
 .long 0x25
 .uleb128 0x5
 .string "u16"
 .byte 0xa
 .byte 0x45
 .long 0x3e
 .uleb128 0x5
 .string "u32"
 .byte 0xa
 .byte 0x46
 .long 0x57
 .uleb128 0x3
 .byte 0x4
 .byte 0x5
 .long .LASF10
 .uleb128 0x3
 .byte 0x4
 .byte 0x7
 .long .LASF11
 .uleb128 0x2
 .long .LASF12
 .byte 0xb
 .byte 0x3a
 .long 0x62
 .uleb128 0x6
 .long .LASF57
 .byte 0x8
 .byte 0x2
 .byte 0x14
 .long 0xde
 .uleb128 0x7
 .string "lo"
 .byte 0x2
 .byte 0x16
 .long 0x62
 .byte 0x2
 .byte 0x23
 .uleb128 0x0
 .uleb128 0x7
 .string "hi"
 .byte 0x2
 .byte 0x17
 .long 0x62
 .byte 0x2
 .byte 0x23
 .uleb128 0x4
 .byte 0x0
 .uleb128 0x2
 .long .LASF13
 .byte 0x2
 .byte 0x18
 .long 0xb7
 .uleb128 0x2
 .long .LASF14
 .byte 0xc
 .byte 0xf1
 .long 0xa5
 .uleb128 0x2
 .long .LASF15
 .byte 0xc
 .byte 0xf3
 .long 0x70
 .uleb128 0x8
 .long .LASF17
 .byte 0xb
 .value 0x122
 .byte 0x1
 .byte 0x3
 .long 0x13e
 .uleb128 0x9
 .string "dev"
 .byte 0xb
 .value 0x122
 .long 0xac
 .uleb128 0x9
 .string "reg"
 .byte 0xb
 .value 0x122
 .long 0x25
 .uleb128 0xa
 .long .LASF16
 .byte 0xb
 .value 0x122
 .long 0x25
 .uleb128 0xb
 .long .LASF19
 .byte 0xb
 .value 0x124
 .long 0x62
 .byte 0x0
 .uleb128 0xc
 .long .LASF18
 .byte 0x4
 .byte 0x2c
 .byte 0x1
 .byte 0x3
 .long 0x162
 .uleb128 0xd
 .long .LASF16
 .byte 0x4
 .byte 0x2c
 .long 0x25
 .uleb128 0xd
 .long .LASF19
 .byte 0x4
 .byte 0x2c
 .long 0x3e
 .byte 0x0
 .uleb128 0xc
 .long .LASF20
 .byte 0xd
 .byte 0x1a
 .byte 0x1
 .byte 0x1
 .long 0x186
 .uleb128 0xe
 .string "dev"
 .byte 0xd
 .byte 0x1a
 .long 0xac
 .uleb128 0xf
 .long .LASF19
 .byte 0xd
 .byte 0x1c
 .long 0x88
 .byte 0x0
 .uleb128 0x8
 .long .LASF21
 .byte 0xb
 .value 0x130
 .byte 0x1
 .byte 0x3
 .long 0x1ad
 .uleb128 0x9
 .string "dev"
 .byte 0xb
 .value 0x130
 .long 0xac
 .uleb128 0xb
 .long .LASF22
 .byte 0xb
 .value 0x132
 .long 0x62
 .byte 0x0
 .uleb128 0x8
 .long .LASF23
 .byte 0xb
 .value 0x136
 .byte 0x1
 .byte 0x3
 .long 0x1d4
 .uleb128 0x9
 .string "dev"
 .byte 0xb
 .value 0x136
 .long 0xac
 .uleb128 0xa
 .long .LASF24
 .byte 0xb
 .value 0x136
 .long 0x69
 .byte 0x0
 .uleb128 0x8
 .long .LASF25
 .byte 0xb
 .value 0x140
 .byte 0x1
 .byte 0x3
 .long 0x207
 .uleb128 0x9
 .string "dev"
 .byte 0xb
 .value 0x140
 .long 0xac
 .uleb128 0xa
 .long .LASF26
 .byte 0xb
 .value 0x140
 .long 0x62
 .uleb128 0xa
 .long .LASF27
 .byte 0xb
 .value 0x140
 .long 0x62
 .byte 0x0
 .uleb128 0xc
 .long .LASF28
 .byte 0xd
 .byte 0x21
 .byte 0x1
 .byte 0x1
 .long 0x22b
 .uleb128 0xe
 .string "dev"
 .byte 0xd
 .byte 0x21
 .long 0xac
 .uleb128 0xf
 .long .LASF19
 .byte 0xd
 .byte 0x23
 .long 0x88
 .byte 0x0
 .uleb128 0x10
 .long .LASF30
 .byte 0x2
 .byte 0x2a
 .byte 0x1
 .long 0xde
 .byte 0x3
 .long 0x253
 .uleb128 0xd
 .long .LASF26
 .byte 0x2
 .byte 0x2a
 .long 0x62
 .uleb128 0xf
 .long .LASF29
 .byte 0x2
 .byte 0x2c
 .long 0xde
 .byte 0x0
 .uleb128 0x11
 .string "inb"
 .byte 0x4
 .byte 0x3b
 .byte 0x1
 .long 0x25
 .byte 0x3
 .long 0x27b
 .uleb128 0xd
 .long .LASF19
 .byte 0x4
 .byte 0x3b
 .long 0x3e
 .uleb128 0xf
 .long .LASF16
 .byte 0x4
 .byte 0x3d
 .long 0x25
 .byte 0x0
 .uleb128 0x8
 .long .LASF31
 .byte 0x7
 .value 0x1cc
 .byte 0x1
 .byte 0x3
 .long 0x2a2
 .uleb128 0x9
 .string "msr"
 .byte 0x7
 .value 0x1cc
 .long 0xe9
 .uleb128 0xa
 .long .LASF32
 .byte 0x7
 .value 0x1cc
 .long 0xf4
 .byte 0x0
 .uleb128 0xc
 .long .LASF33
 .byte 0x7
 .byte 0x59
 .byte 0x1
 .byte 0x3
 .long 0x2c6
 .uleb128 0xd
 .long .LASF34
 .byte 0x7
 .byte 0x59
 .long 0x49
 .uleb128 0xd
 .long .LASF35
 .byte 0x7
 .byte 0x59
 .long 0xa5
 .byte 0x0
 .uleb128 0x10
 .long .LASF36
 .byte 0x7
 .byte 0x3a
 .byte 0x1
 .long 0xa5
 .byte 0x3
 .long 0x2ee
 .uleb128 0xd
 .long .LASF34
 .byte 0x7
 .byte 0x3a
 .long 0x49
 .uleb128 0xf
 .long .LASF16
 .byte 0x7
 .byte 0x3c
 .long 0xa5
 .byte 0x0
 .uleb128 0xc
 .long .LASF37
 .byte 0xd
 .byte 0x27
 .byte 0x1
 .byte 0x1
 .long 0x312
 .uleb128 0xe
 .string "dev"
 .byte 0xd
 .byte 0x27
 .long 0xac
 .uleb128 0xd
 .long .LASF27
 .byte 0xd
 .byte 0x27
 .long 0x88
 .byte 0x0
 .uleb128 0xc
 .long .LASF38
 .byte 0x8
 .byte 0x4
 .byte 0x1
 .byte 0x1
 .long 0x32b
 .uleb128 0xd
 .long .LASF39
 .byte 0x8
 .byte 0x4
 .long 0x93
 .byte 0x0
 .uleb128 0x10
 .long .LASF40
 .byte 0x9
 .byte 0x33
 .byte 0x1
 .long 0x62
 .byte 0x3
 .long 0x352
 .uleb128 0xe
 .string "op"
 .byte 0x9
 .byte 0x33
 .long 0x62
 .uleb128 0x12
 .string "eax"
 .byte 0x9
 .byte 0x35
 .long 0x62
 .byte 0x0
 .uleb128 0x13
 .long .LASF58
 .byte 0x1
 .byte 0x3
 .byte 0x1
 .long 0x69
 .long .LFB150
 .long .LFE150
 .byte 0x2
 .byte 0x74
 .sleb128 4
 .long 0x3ad
 .uleb128 0x14
 .string "bsp"
 .byte 0x1
 .byte 0x5
 .long 0x69
 .long .LLST0
 .uleb128 0x12
 .string "msr"
 .byte 0x1
 .byte 0x6
 .long 0xde
 .uleb128 0x15
 .long 0x22b
 .long .LBB212
 .long .LBE212
 .byte 0x1
 .byte 0x7
 .uleb128 0x16
 .long 0x23c
 .byte 0x1b
 .uleb128 0x17
 .long .LBB213
 .long .LBE213
 .uleb128 0x18
 .long 0x247
 .byte 0x0
 .byte 0x0
 .byte 0x0
 .uleb128 0x19
 .byte 0x1
 .long .LASF41
 .byte 0x3
 .byte 0x1a
 .byte 0x1
 .long .LFB151
 .long .LFE151
 .byte 0x2
 .byte 0x74
 .sleb128 4
 .long 0x462
 .uleb128 0x1a
 .long 0x13e
 .long .LBB214
 .long .LBE214
 .byte 0x3
 .byte 0x1d
 .long 0x3e5
 .uleb128 0x16
 .long 0x156
 .byte 0x43
 .uleb128 0x16
 .long 0x14b
 .byte 0x36
 .byte 0x0
 .uleb128 0x1a
 .long 0x13e
 .long .LBB216
 .long .LBE216
 .byte 0x3
 .byte 0x1e
 .long 0x405
 .uleb128 0x16
 .long 0x156
 .byte 0x40
 .uleb128 0x16
 .long 0x14b
 .byte 0x0
 .byte 0x0
 .uleb128 0x1a
 .long 0x13e
 .long .LBB218
 .long .LBE218
 .byte 0x3
 .byte 0x1f
 .long 0x425
 .uleb128 0x16
 .long 0x156
 .byte 0x40
 .uleb128 0x16
 .long 0x14b
 .byte 0x0
 .byte 0x0
 .uleb128 0x1a
 .long 0x13e
 .long .LBB220
 .long .LBE220
 .byte 0x3
 .byte 0x22
 .long 0x445
 .uleb128 0x16
 .long 0x156
 .byte 0x43
 .uleb128 0x16
 .long 0x14b
 .byte 0x56
 .byte 0x0
 .uleb128 0x15
 .long 0x13e
 .long .LBB222
 .long .LBE222
 .byte 0x3
 .byte 0x23
 .uleb128 0x16
 .long 0x156
 .byte 0x41
 .uleb128 0x16
 .long 0x14b
 .byte 0x12
 .byte 0x0
 .byte 0x0
 .uleb128 0x19
 .byte 0x1
 .long .LASF42
 .byte 0x5
 .byte 0x3b
 .byte 0x1
 .long .LFB152
 .long .LFE152
 .byte 0x2
 .byte 0x74
 .sleb128 4
 .long 0x5b7
 .uleb128 0x1a
 .long 0x13e
 .long .LBB224
 .long .LBE224
 .byte 0x5
 .byte 0x47
 .long 0x49a
 .uleb128 0x16
 .long 0x156
 .byte 0x20
 .uleb128 0x16
 .long 0x14b
 .byte 0x11
 .byte 0x0
 .uleb128 0x1a
 .long 0x13e
 .long .LBB226
 .long .LBE226
 .byte 0x5
 .byte 0x48
 .long 0x4ba
 .uleb128 0x16
 .long 0x156
 .byte 0xa0
 .uleb128 0x16
 .long 0x14b
 .byte 0x11
 .byte 0x0
 .uleb128 0x1a
 .long 0x13e
 .long .LBB228
 .long .LBE228
 .byte 0x5
 .byte 0x4b
 .long 0x4da
 .uleb128 0x16
 .long 0x156
 .byte 0x21
 .uleb128 0x16
 .long 0x14b
 .byte 0x20
 .byte 0x0
 .uleb128 0x1a
 .long 0x13e
 .long .LBB230
 .long .LBE230
 .byte 0x5
 .byte 0x4c
 .long 0x4fa
 .uleb128 0x16
 .long 0x156
 .byte 0xa1
 .uleb128 0x16
 .long 0x14b
 .byte 0x28
 .byte 0x0
 .uleb128 0x1a
 .long 0x13e
 .long .LBB232
 .long .LBE232
 .byte 0x5
 .byte 0x53
 .long 0x51a
 .uleb128 0x16
 .long 0x156
 .byte 0x21
 .uleb128 0x16
 .long 0x14b
 .byte 0x4
 .byte 0x0
 .uleb128 0x1a
 .long 0x13e
 .long .LBB234
 .long .LBE234
 .byte 0x5
 .byte 0x54
 .long 0x53a
 .uleb128 0x16
 .long 0x156
 .byte 0xa1
 .uleb128 0x16
 .long 0x14b
 .byte 0x2
 .byte 0x0
 .uleb128 0x1a
 .long 0x13e
 .long .LBB236
 .long .LBE236
 .byte 0x5
 .byte 0x5b
 .long 0x55a
 .uleb128 0x16
 .long 0x156
 .byte 0x21
 .uleb128 0x16
 .long 0x14b
 .byte 0x1
 .byte 0x0
 .uleb128 0x1a
 .long 0x13e
 .long .LBB238
 .long .LBE238
 .byte 0x5
 .byte 0x5c
 .long 0x57a
 .uleb128 0x16
 .long 0x156
 .byte 0xa1
 .uleb128 0x16
 .long 0x14b
 .byte 0x1
 .byte 0x0
 .uleb128 0x1a
 .long 0x13e
 .long .LBB240
 .long .LBE240
 .byte 0x5
 .byte 0x63
 .long 0x59a
 .uleb128 0x16
 .long 0x156
 .byte 0xa1
 .uleb128 0x1b
 .long 0x14b
 .sleb128 -1
 .byte 0x0
 .uleb128 0x15
 .long 0x13e
 .long .LBB242
 .long .LBE242
 .byte 0x5
 .byte 0x64
 .uleb128 0x16
 .long 0x156
 .byte 0x21
 .uleb128 0x1b
 .long 0x14b
 .sleb128 -5
 .byte 0x0
 .byte 0x0
 .uleb128 0x1c
 .byte 0x1
 .long .LASF43
 .byte 0x5
 .byte 0x70
 .byte 0x1
 .long .LFB153
 .long .LFE153
 .long .LLST1
 .long 0x6a4
 .uleb128 0x1d
 .long .LASF44
 .byte 0x5
 .byte 0x70
 .long 0x69
 .byte 0x2
 .byte 0x91
 .sleb128 0
 .uleb128 0x1d
 .long .LASF45
 .byte 0x5
 .byte 0x70
 .long 0x69
 .byte 0x2
 .byte 0x91
 .sleb128 4
 .uleb128 0x1e
 .long .LASF46
 .byte 0x5
 .byte 0x72
 .long 0x88
 .long .LLST2
 .uleb128 0x1f
 .long .LASF47
 .long 0x6bb
 .byte 0x1
 .byte 0x5
 .byte 0x3
 .long __func__.3515
 .uleb128 0x20
 .long 0x253
 .long .LBB244
 .long .Ldebug_ranges0+0x0
 .byte 0x5
 .byte 0x72
 .long 0x635
 .uleb128 0x21
 .long 0x264
 .value 0x4d0
 .uleb128 0x22
 .long .Ldebug_ranges0+0x18
 .uleb128 0x23
 .long 0x26f
 .long .LLST3
 .byte 0x0
 .byte 0x0
 .uleb128 0x1a
 .long 0x253
 .long .LBB248
 .long .LBE248
 .byte 0x5
 .byte 0x72
 .long 0x663
 .uleb128 0x21
 .long 0x264
 .value 0x4d1
 .uleb128 0x17
 .long .LBB249
 .long .LBE249
 .uleb128 0x23
 .long 0x26f
 .long .LLST4
 .byte 0x0
 .byte 0x0
 .uleb128 0x1a
 .long 0x13e
 .long .LBB250
 .long .LBE250
 .byte 0x5
 .byte 0x7c
 .long 0x687
 .uleb128 0x21
 .long 0x156
 .value 0x4d0
 .uleb128 0x24
 .long 0x14b
 .long .LLST5
 .byte 0x0
 .uleb128 0x15
 .long 0x13e
 .long .LBB252
 .long .LBE252
 .byte 0x5
 .byte 0x7d
 .uleb128 0x21
 .long 0x156
 .value 0x4d1
 .uleb128 0x25
 .long 0x14b
 .byte 0x0
 .byte 0x0
 .uleb128 0x26
 .long 0x6b4
 .long 0x6b4
 .uleb128 0x27
 .long 0xa5
 .byte 0x1b
 .byte 0x0
 .uleb128 0x3
 .byte 0x1
 .byte 0x6
 .long .LASF48
 .uleb128 0x28
 .long 0x6a4
 .uleb128 0x1c
 .byte 0x1
 .long .LASF49
 .byte 0x6
 .byte 0x2d
 .byte 0x1
 .long .LFB154
 .long .LFE154
 .long .LLST6
 .long 0xde0
 .uleb128 0x1d
 .long .LASF39
 .byte 0x6
 .byte 0x2d
 .long 0xa5
 .byte 0x2
 .byte 0x91
 .sleb128 0
 .uleb128 0x1d
 .long .LASF50
 .byte 0x6
 .byte 0x2d
 .long 0xa5
 .byte 0x2
 .byte 0x91
 .sleb128 4
 .uleb128 0x14
 .string "val"
 .byte 0x6
 .byte 0x2f
 .long 0x93
 .long .LLST7
 .uleb128 0xf
 .long .LASF51
 .byte 0x6
 .byte 0x30
 .long 0x7e
 .uleb128 0x20
 .long 0x27b
 .long .LBB254
 .long .Ldebug_ranges0+0x30
 .byte 0x6
 .byte 0x34
 .long 0x737
 .uleb128 0x29
 .long 0x295
 .long 0xffc00005
 .long 0x0
 .uleb128 0x21
 .long 0x289
 .value 0x20c
 .byte 0x0
 .uleb128 0x1a
 .long 0x27b
 .long .LBB258
 .long .LBE258
 .byte 0x6
 .byte 0x35
 .long 0x75f
 .uleb128 0x29
 .long 0x295
 .long 0xffc00800
 .long 0xf
 .uleb128 0x21
 .long 0x289
 .value 0x20d
 .byte 0x0
 .uleb128 0x1a
 .long 0x27b
 .long .LBB260
 .long .LBE260
 .byte 0x6
 .byte 0x38
 .long 0x783
 .uleb128 0x16
 .long 0x295
 .byte 0x0
 .uleb128 0x1b
 .long 0x289
 .sleb128 -1073676190
 .byte 0x0
 .uleb128 0x2a
 .long .LBB262
 .long .LBE262
 .long 0x818
 .uleb128 0x1e
 .long .LASF51
 .byte 0x6
 .byte 0x3c
 .long 0x7e
 .long .LLST8
 .uleb128 0x1a
 .long 0x13e
 .long .LBB263
 .long .LBE263
 .byte 0x6
 .byte 0x3e
 .long 0x7c5
 .uleb128 0x24
 .long 0x156
 .long .LLST9
 .uleb128 0x24
 .long 0x14b
 .long .LLST10
 .byte 0x0
 .uleb128 0x1a
 .long 0x253
 .long .LBB265
 .long .LBE265
 .byte 0x6
 .byte 0x3f
 .long 0x7f5
 .uleb128 0x24
 .long 0x264
 .long .LLST11
 .uleb128 0x17
 .long .LBB266
 .long .LBE266
 .uleb128 0x23
 .long 0x26f
 .long .LLST12
 .byte 0x0
 .byte 0x0
 .uleb128 0x15
 .long 0x13e
 .long .LBB267
 .long .LBE267
 .byte 0x6
 .byte 0x42
 .uleb128 0x24
 .long 0x156
 .long .LLST13
 .uleb128 0x24
 .long 0x14b
 .long .LLST14
 .byte 0x0
 .byte 0x0
 .uleb128 0x1a
 .long 0x2a2
 .long .LBB269
 .long .LBE269
 .byte 0x6
 .byte 0x4c
 .long 0x83e
 .uleb128 0x24
 .long 0x2ba
 .long .LLST15
 .uleb128 0x24
 .long 0x2af
 .long .LLST16
 .byte 0x0
 .uleb128 0x1a
 .long 0x2c6
 .long .LBB271
 .long .LBE271
 .byte 0x6
 .byte 0x4d
 .long 0x86e
 .uleb128 0x24
 .long 0x2d7
 .long .LLST17
 .uleb128 0x17
 .long .LBB272
 .long .LBE272
 .uleb128 0x23
 .long 0x2e2
 .long .LLST18
 .byte 0x0
 .byte 0x0
 .uleb128 0x1a
 .long 0x2a2
 .long .LBB273
 .long .LBE273
 .byte 0x6
 .byte 0x4d
 .long 0x894
 .uleb128 0x24
 .long 0x2ba
 .long .LLST19
 .uleb128 0x24
 .long 0x2af
 .long .LLST20
 .byte 0x0
 .uleb128 0x2a
 .long .LBB275
 .long .LBE275
 .long 0x952
 .uleb128 0x1e
 .long .LASF52
 .byte 0x6
 .byte 0x53
 .long 0xde0
 .long .LLST21
 .uleb128 0xf
 .long .LASF53
 .byte 0x6
 .byte 0x54
 .long 0x93
 .uleb128 0x1a
 .long 0x2a2
 .long .LBB276
 .long .LBE276
 .byte 0x6
 .byte 0x55
 .long 0x8e1
 .uleb128 0x24
 .long 0x2ba
 .long .LLST22
 .uleb128 0x24
 .long 0x2af
 .long .LLST23
 .byte 0x0
 .uleb128 0x1a
 .long 0x2c6
 .long .LBB278
 .long .LBE278
 .byte 0x6
 .byte 0x56
 .long 0x90d
 .uleb128 0x24
 .long 0x2d7
 .long .LLST24
 .uleb128 0x17
 .long .LBB279
 .long .LBE279
 .uleb128 0x18
 .long 0x2e2
 .byte 0x0
 .byte 0x0
 .uleb128 0x1a
 .long 0x2a2
 .long .LBB280
 .long .LBE280
 .byte 0x6
 .byte 0x57
 .long 0x933
 .uleb128 0x24
 .long 0x2ba
 .long .LLST25
 .uleb128 0x24
 .long 0x2af
 .long .LLST26
 .byte 0x0
 .uleb128 0x15
 .long 0x2a2
 .long .LBB282
 .long .LBE282
 .byte 0x6
 .byte 0x5a
 .uleb128 0x25
 .long 0x2ba
 .uleb128 0x24
 .long 0x2af
 .long .LLST27
 .byte 0x0
 .byte 0x0
 .uleb128 0x1a
 .long 0x2ee
 .long .LBB284
 .long .LBE284
 .byte 0x6
 .byte 0x62
 .long 0xd9a
 .uleb128 0x24
 .long 0x306
 .long .LLST28
 .uleb128 0x24
 .long 0x2fb
 .long .LLST29
 .uleb128 0x1a
 .long 0x162
 .long .LBB285
 .long .LBE285
 .byte 0xd
 .byte 0x29
 .long 0x9ef
 .uleb128 0x24
 .long 0x16f
 .long .LLST30
 .uleb128 0x17
 .long .LBB286
 .long .LBE286
 .uleb128 0x23
 .long 0x17a
 .long .LLST31
 .uleb128 0x1a
 .long 0x13e
 .long .LBB287
 .long .LBE287
 .byte 0xd
 .byte 0x1d
 .long 0x9cb
 .uleb128 0x24
 .long 0x156
 .long .LLST32
 .uleb128 0x24
 .long 0x14b
 .long .LLST33
 .byte 0x0
 .uleb128 0x15
 .long 0x13e
 .long .LBB289
 .long .LBE289
 .byte 0xd
 .byte 0x1e
 .uleb128 0x24
 .long 0x156
 .long .LLST34
 .uleb128 0x24
 .long 0x14b
 .long .LLST35
 .byte 0x0
 .byte 0x0
 .byte 0x0
 .uleb128 0x1a
 .long 0x186
 .long .LBB291
 .long .LBE291
 .byte 0xd
 .byte 0x2a
 .long 0xaa8
 .uleb128 0x24
 .long 0x194
 .long .LLST36
 .uleb128 0x17
 .long .LBB292
 .long .LBE292
 .uleb128 0x23
 .long 0x1a0
 .long .LLST37
 .uleb128 0x2b
 .long 0xff
 .long .LBB293
 .long .LBE293
 .byte 0xb
 .value 0x133
 .uleb128 0x24
 .long 0x125
 .long .LLST38
 .uleb128 0x24
 .long 0x119
 .long .LLST39
 .uleb128 0x24
 .long 0x10d
 .long .LLST40
 .uleb128 0x17
 .long .LBB294
 .long .LBE294
 .uleb128 0x23
 .long 0x131
 .long .LLST41
 .uleb128 0x2c
 .long 0x13e
 .long .LBB295
 .long .LBE295
 .byte 0xb
 .value 0x125
 .long 0xa81
 .uleb128 0x24
 .long 0x156
 .long .LLST42
 .uleb128 0x24
 .long 0x14b
 .long .LLST43
 .byte 0x0
 .uleb128 0x2b
 .long 0x13e
 .long .LBB297
 .long .LBE297
 .byte 0xb
 .value 0x126
 .uleb128 0x24
 .long 0x156
 .long .LLST44
 .uleb128 0x24
 .long 0x14b
 .long .LLST45
 .byte 0x0
 .byte 0x0
 .byte 0x0
 .byte 0x0
 .byte 0x0
 .uleb128 0x1a
 .long 0x1ad
 .long .LBB299
 .long .LBE299
 .byte 0xd
 .byte 0x2b
 .long 0xb57
 .uleb128 0x24
 .long 0x1c7
 .long .LLST46
 .uleb128 0x24
 .long 0x1bb
 .long .LLST47
 .uleb128 0x2b
 .long 0xff
 .long .LBB300
 .long .LBE300
 .byte 0xb
 .value 0x138
 .uleb128 0x24
 .long 0x119
 .long .LLST48
 .uleb128 0x24
 .long 0x125
 .long .LLST49
 .uleb128 0x24
 .long 0x10d
 .long .LLST50
 .uleb128 0x17
 .long .LBB301
 .long .LBE301
 .uleb128 0x23
 .long 0x131
 .long .LLST51
 .uleb128 0x2c
 .long 0x13e
 .long .LBB302
 .long .LBE302
 .byte 0xb
 .value 0x125
 .long 0xb31
 .uleb128 0x24
 .long 0x156
 .long .LLST52
 .uleb128 0x24
 .long 0x14b
 .long .LLST53
 .byte 0x0
 .uleb128 0x2b
 .long 0x13e
 .long .LBB304
 .long .LBE304
 .byte 0xb
 .value 0x126
 .uleb128 0x24
 .long 0x156
 .long .LLST54
 .uleb128 0x24
 .long 0x14b
 .long .LLST55
 .byte 0x0
 .byte 0x0
 .byte 0x0
 .byte 0x0
 .uleb128 0x1a
 .long 0x1d4
 .long .LBB306
 .long .LBE306
 .byte 0xd
 .byte 0x2c
 .long 0xc9c
 .uleb128 0x24
 .long 0x1fa
 .long .LLST56
 .uleb128 0x24
 .long 0x1ee
 .long .LLST57
 .uleb128 0x24
 .long 0x1e2
 .long .LLST58
 .uleb128 0x2c
 .long 0xff
 .long .LBB307
 .long .LBE307
 .byte 0xb
 .value 0x142
 .long 0xc12
 .uleb128 0x24
 .long 0x125
 .long .LLST59
 .uleb128 0x24
 .long 0x10d
 .long .LLST60
 .uleb128 0x24
 .long 0x119
 .long .LLST61
 .uleb128 0x17
 .long .LBB308
 .long .LBE308
 .uleb128 0x23
 .long 0x131
 .long .LLST62
 .uleb128 0x2c
 .long 0x13e
 .long .LBB309
 .long .LBE309
 .byte 0xb
 .value 0x125
 .long 0xbed
 .uleb128 0x24
 .long 0x156
 .long .LLST63
 .uleb128 0x24
 .long 0x14b
 .long .LLST64
 .byte 0x0
 .uleb128 0x2b
 .long 0x13e
 .long .LBB311
 .long .LBE311
 .byte 0xb
 .value 0x126
 .uleb128 0x24
 .long 0x156
 .long .LLST65
 .uleb128 0x24
 .long 0x14b
 .long .LLST66
 .byte 0x0
 .byte 0x0
 .byte 0x0
 .uleb128 0x2b
 .long 0xff
 .long .LBB313
 .long .LBE313
 .byte 0xb
 .value 0x143
 .uleb128 0x24
 .long 0x125
 .long .LLST67
 .uleb128 0x24
 .long 0x119
 .long .LLST68
 .uleb128 0x24
 .long 0x10d
 .long .LLST69
 .uleb128 0x17
 .long .LBB314
 .long .LBE314
 .uleb128 0x23
 .long 0x131
 .long .LLST70
 .uleb128 0x2c
 .long 0x13e
 .long .LBB315
 .long .LBE315
 .byte 0xb
 .value 0x125
 .long 0xc76
 .uleb128 0x24
 .long 0x156
 .long .LLST71
 .uleb128 0x24
 .long 0x14b
 .long .LLST72
 .byte 0x0
 .uleb128 0x2b
 .long 0x13e
 .long .LBB317
 .long .LBE317
 .byte 0xb
 .value 0x126
 .uleb128 0x24
 .long 0x156
 .long .LLST73
 .uleb128 0x24
 .long 0x14b
 .long .LLST74
 .byte 0x0
 .byte 0x0
 .byte 0x0
 .byte 0x0
 .uleb128 0x1a
 .long 0x1ad
 .long .LBB319
 .long .LBE319
 .byte 0xd
 .byte 0x2d
 .long 0xd4b
 .uleb128 0x24
 .long 0x1c7
 .long .LLST75
 .uleb128 0x24
 .long 0x1bb
 .long .LLST76
 .uleb128 0x2b
 .long 0xff
 .long .LBB320
 .long .LBE320
 .byte 0xb
 .value 0x138
 .uleb128 0x24
 .long 0x119
 .long .LLST77
 .uleb128 0x24
 .long 0x125
 .long .LLST78
 .uleb128 0x24
 .long 0x10d
 .long .LLST79
 .uleb128 0x17
 .long .LBB321
 .long .LBE321
 .uleb128 0x23
 .long 0x131
 .long .LLST80
 .uleb128 0x2c
 .long 0x13e
 .long .LBB322
 .long .LBE322
 .byte 0xb
 .value 0x125
 .long 0xd25
 .uleb128 0x24
 .long 0x156
 .long .LLST81
 .uleb128 0x24
 .long 0x14b
 .long .LLST82
 .byte 0x0
 .uleb128 0x2b
 .long 0x13e
 .long .LBB324
 .long .LBE324
 .byte 0xb
 .value 0x126
 .uleb128 0x24
 .long 0x156
 .long .LLST83
 .uleb128 0x24
 .long 0x14b
 .long .LLST84
 .byte 0x0
 .byte 0x0
 .byte 0x0
 .byte 0x0
 .uleb128 0x15
 .long 0x207
 .long .LBB326
 .long .LBE326
 .byte 0xd
 .byte 0x2e
 .uleb128 0x24
 .long 0x214
 .long .LLST85
 .uleb128 0x17
 .long .LBB327
 .long .LBE327
 .uleb128 0x23
 .long 0x21f
 .long .LLST86
 .uleb128 0x15
 .long 0x13e
 .long .LBB328
 .long .LBE328
 .byte 0xd
 .byte 0x24
 .uleb128 0x24
 .long 0x156
 .long .LLST87
 .uleb128 0x24
 .long 0x14b
 .long .LLST88
 .byte 0x0
 .byte 0x0
 .byte 0x0
 .byte 0x0
 .uleb128 0x1a
 .long 0x312
 .long .LBB330
 .long .LBE330
 .byte 0x6
 .byte 0x68
 .long 0xdb6
 .uleb128 0x2d
 .long 0x31f
 .byte 0x2
 .byte 0x91
 .sleb128 0
 .byte 0x0
 .uleb128 0x15
 .long 0x32b
 .long .LBB332
 .long .LBE332
 .byte 0x6
 .byte 0x6b
 .uleb128 0x16
 .long 0x33c
 .byte 0x1
 .uleb128 0x17
 .long .LBB333
 .long .LBE333
 .uleb128 0x23
 .long 0x346
 .long .LLST89
 .byte 0x0
 .byte 0x0
 .byte 0x0
 .uleb128 0x2e
 .byte 0x4
 .long 0xde6
 .uleb128 0x2f
 .long 0x93
 .byte 0x0
 .section .debug_abbrev
 .uleb128 0x1
 .uleb128 0x11
 .byte 0x1
 .uleb128 0x25
 .uleb128 0xe
 .uleb128 0x13
 .uleb128 0xb
 .uleb128 0x3
 .uleb128 0xe
 .uleb128 0x1b
 .uleb128 0xe
 .uleb128 0x11
 .uleb128 0x1
 .uleb128 0x12
 .uleb128 0x1
 .uleb128 0x10
 .uleb128 0x6
 .byte 0x0
 .byte 0x0
 .uleb128 0x2
 .uleb128 0x16
 .byte 0x0
 .uleb128 0x3
 .uleb128 0xe
 .uleb128 0x3a
 .uleb128 0xb
 .uleb128 0x3b
 .uleb128 0xb
 .uleb128 0x49
 .uleb128 0x13
 .byte 0x0
 .byte 0x0
 .uleb128 0x3
 .uleb128 0x24
 .byte 0x0
 .uleb128 0xb
 .uleb128 0xb
 .uleb128 0x3e
 .uleb128 0xb
 .uleb128 0x3
 .uleb128 0xe
 .byte 0x0
 .byte 0x0
 .uleb128 0x4
 .uleb128 0x24
 .byte 0x0
 .uleb128 0xb
 .uleb128 0xb
 .uleb128 0x3e
 .uleb128 0xb
 .uleb128 0x3
 .uleb128 0x8
 .byte 0x0
 .byte 0x0
 .uleb128 0x5
 .uleb128 0x16
 .byte 0x0
 .uleb128 0x3
 .uleb128 0x8
 .uleb128 0x3a
 .uleb128 0xb
 .uleb128 0x3b
 .uleb128 0xb
 .uleb128 0x49
 .uleb128 0x13
 .byte 0x0
 .byte 0x0
 .uleb128 0x6
 .uleb128 0x13
 .byte 0x1
 .uleb128 0x3
 .uleb128 0xe
 .uleb128 0xb
 .uleb128 0xb
 .uleb128 0x3a
 .uleb128 0xb
 .uleb128 0x3b
 .uleb128 0xb
 .uleb128 0x1
 .uleb128 0x13
 .byte 0x0
 .byte 0x0
 .uleb128 0x7
 .uleb128 0xd
 .byte 0x0
 .uleb128 0x3
 .uleb128 0x8
 .uleb128 0x3a
 .uleb128 0xb
 .uleb128 0x3b
 .uleb128 0xb
 .uleb128 0x49
 .uleb128 0x13
 .uleb128 0x38
 .uleb128 0xa
 .byte 0x0
 .byte 0x0
 .uleb128 0x8
 .uleb128 0x2e
 .byte 0x1
 .uleb128 0x3
 .uleb128 0xe
 .uleb128 0x3a
 .uleb128 0xb
 .uleb128 0x3b
 .uleb128 0x5
 .uleb128 0x27
 .uleb128 0xc
 .uleb128 0x20
 .uleb128 0xb
 .uleb128 0x1
 .uleb128 0x13
 .byte 0x0
 .byte 0x0
 .uleb128 0x9
 .uleb128 0x5
 .byte 0x0
 .uleb128 0x3
 .uleb128 0x8
 .uleb128 0x3a
 .uleb128 0xb
 .uleb128 0x3b
 .uleb128 0x5
 .uleb128 0x49
 .uleb128 0x13
 .byte 0x0
 .byte 0x0
 .uleb128 0xa
 .uleb128 0x5
 .byte 0x0
 .uleb128 0x3
 .uleb128 0xe
 .uleb128 0x3a
 .uleb128 0xb
 .uleb128 0x3b
 .uleb128 0x5
 .uleb128 0x49
 .uleb128 0x13
 .byte 0x0
 .byte 0x0
 .uleb128 0xb
 .uleb128 0x34
 .byte 0x0
 .uleb128 0x3
 .uleb128 0xe
 .uleb128 0x3a
 .uleb128 0xb
 .uleb128 0x3b
 .uleb128 0x5
 .uleb128 0x49
 .uleb128 0x13
 .byte 0x0
 .byte 0x0
 .uleb128 0xc
 .uleb128 0x2e
 .byte 0x1
 .uleb128 0x3
 .uleb128 0xe
 .uleb128 0x3a
 .uleb128 0xb
 .uleb128 0x3b
 .uleb128 0xb
 .uleb128 0x27
 .uleb128 0xc
 .uleb128 0x20
 .uleb128 0xb
 .uleb128 0x1
 .uleb128 0x13
 .byte 0x0
 .byte 0x0
 .uleb128 0xd
 .uleb128 0x5
 .byte 0x0
 .uleb128 0x3
 .uleb128 0xe
 .uleb128 0x3a
 .uleb128 0xb
 .uleb128 0x3b
 .uleb128 0xb
 .uleb128 0x49
 .uleb128 0x13
 .byte 0x0
 .byte 0x0
 .uleb128 0xe
 .uleb128 0x5
 .byte 0x0
 .uleb128 0x3
 .uleb128 0x8
 .uleb128 0x3a
 .uleb128 0xb
 .uleb128 0x3b
 .uleb128 0xb
 .uleb128 0x49
 .uleb128 0x13
 .byte 0x0
 .byte 0x0
 .uleb128 0xf
 .uleb128 0x34
 .byte 0x0
 .uleb128 0x3
 .uleb128 0xe
 .uleb128 0x3a
 .uleb128 0xb
 .uleb128 0x3b
 .uleb128 0xb
 .uleb128 0x49
 .uleb128 0x13
 .byte 0x0
 .byte 0x0
 .uleb128 0x10
 .uleb128 0x2e
 .byte 0x1
 .uleb128 0x3
 .uleb128 0xe
 .uleb128 0x3a
 .uleb128 0xb
 .uleb128 0x3b
 .uleb128 0xb
 .uleb128 0x27
 .uleb128 0xc
 .uleb128 0x49
 .uleb128 0x13
 .uleb128 0x20
 .uleb128 0xb
 .uleb128 0x1
 .uleb128 0x13
 .byte 0x0
 .byte 0x0
 .uleb128 0x11
 .uleb128 0x2e
 .byte 0x1
 .uleb128 0x3
 .uleb128 0x8
 .uleb128 0x3a
 .uleb128 0xb
 .uleb128 0x3b
 .uleb128 0xb
 .uleb128 0x27
 .uleb128 0xc
 .uleb128 0x49
 .uleb128 0x13
 .uleb128 0x20
 .uleb128 0xb
 .uleb128 0x1
 .uleb128 0x13
 .byte 0x0
 .byte 0x0
 .uleb128 0x12
 .uleb128 0x34
 .byte 0x0
 .uleb128 0x3
 .uleb128 0x8
 .uleb128 0x3a
 .uleb128 0xb
 .uleb128 0x3b
 .uleb128 0xb
 .uleb128 0x49
 .uleb128 0x13
 .byte 0x0
 .byte 0x0
 .uleb128 0x13
 .uleb128 0x2e
 .byte 0x1
 .uleb128 0x3
 .uleb128 0xe
 .uleb128 0x3a
 .uleb128 0xb
 .uleb128 0x3b
 .uleb128 0xb
 .uleb128 0x27
 .uleb128 0xc
 .uleb128 0x49
 .uleb128 0x13
 .uleb128 0x11
 .uleb128 0x1
 .uleb128 0x12
 .uleb128 0x1
 .uleb128 0x40
 .uleb128 0xa
 .uleb128 0x1
 .uleb128 0x13
 .byte 0x0
 .byte 0x0
 .uleb128 0x14
 .uleb128 0x34
 .byte 0x0
 .uleb128 0x3
 .uleb128 0x8
 .uleb128 0x3a
 .uleb128 0xb
 .uleb128 0x3b
 .uleb128 0xb
 .uleb128 0x49
 .uleb128 0x13
 .uleb128 0x2
 .uleb128 0x6
 .byte 0x0
 .byte 0x0
 .uleb128 0x15
 .uleb128 0x1d
 .byte 0x1
 .uleb128 0x31
 .uleb128 0x13
 .uleb128 0x11
 .uleb128 0x1
 .uleb128 0x12
 .uleb128 0x1
 .uleb128 0x58
 .uleb128 0xb
 .uleb128 0x59
 .uleb128 0xb
 .byte 0x0
 .byte 0x0
 .uleb128 0x16
 .uleb128 0x5
 .byte 0x0
 .uleb128 0x31
 .uleb128 0x13
 .uleb128 0x1c
 .uleb128 0xb
 .byte 0x0
 .byte 0x0
 .uleb128 0x17
 .uleb128 0xb
 .byte 0x1
 .uleb128 0x11
 .uleb128 0x1
 .uleb128 0x12
 .uleb128 0x1
 .byte 0x0
 .byte 0x0
 .uleb128 0x18
 .uleb128 0x34
 .byte 0x0
 .uleb128 0x31
 .uleb128 0x13
 .byte 0x0
 .byte 0x0
 .uleb128 0x19
 .uleb128 0x2e
 .byte 0x1
 .uleb128 0x3f
 .uleb128 0xc
 .uleb128 0x3
 .uleb128 0xe
 .uleb128 0x3a
 .uleb128 0xb
 .uleb128 0x3b
 .uleb128 0xb
 .uleb128 0x27
 .uleb128 0xc
 .uleb128 0x11
 .uleb128 0x1
 .uleb128 0x12
 .uleb128 0x1
 .uleb128 0x40
 .uleb128 0xa
 .uleb128 0x1
 .uleb128 0x13
 .byte 0x0
 .byte 0x0
 .uleb128 0x1a
 .uleb128 0x1d
 .byte 0x1
 .uleb128 0x31
 .uleb128 0x13
 .uleb128 0x11
 .uleb128 0x1
 .uleb128 0x12
 .uleb128 0x1
 .uleb128 0x58
 .uleb128 0xb
 .uleb128 0x59
 .uleb128 0xb
 .uleb128 0x1
 .uleb128 0x13
 .byte 0x0
 .byte 0x0
 .uleb128 0x1b
 .uleb128 0x5
 .byte 0x0
 .uleb128 0x31
 .uleb128 0x13
 .uleb128 0x1c
 .uleb128 0xd
 .byte 0x0
 .byte 0x0
 .uleb128 0x1c
 .uleb128 0x2e
 .byte 0x1
 .uleb128 0x3f
 .uleb128 0xc
 .uleb128 0x3
 .uleb128 0xe
 .uleb128 0x3a
 .uleb128 0xb
 .uleb128 0x3b
 .uleb128 0xb
 .uleb128 0x27
 .uleb128 0xc
 .uleb128 0x11
 .uleb128 0x1
 .uleb128 0x12
 .uleb128 0x1
 .uleb128 0x40
 .uleb128 0x6
 .uleb128 0x1
 .uleb128 0x13
 .byte 0x0
 .byte 0x0
 .uleb128 0x1d
 .uleb128 0x5
 .byte 0x0
 .uleb128 0x3
 .uleb128 0xe
 .uleb128 0x3a
 .uleb128 0xb
 .uleb128 0x3b
 .uleb128 0xb
 .uleb128 0x49
 .uleb128 0x13
 .uleb128 0x2
 .uleb128 0xa
 .byte 0x0
 .byte 0x0
 .uleb128 0x1e
 .uleb128 0x34
 .byte 0x0
 .uleb128 0x3
 .uleb128 0xe
 .uleb128 0x3a
 .uleb128 0xb
 .uleb128 0x3b
 .uleb128 0xb
 .uleb128 0x49
 .uleb128 0x13
 .uleb128 0x2
 .uleb128 0x6
 .byte 0x0
 .byte 0x0
 .uleb128 0x1f
 .uleb128 0x34
 .byte 0x0
 .uleb128 0x3
 .uleb128 0xe
 .uleb128 0x49
 .uleb128 0x13
 .uleb128 0x34
 .uleb128 0xc
 .uleb128 0x2
 .uleb128 0xa
 .byte 0x0
 .byte 0x0
 .uleb128 0x20
 .uleb128 0x1d
 .byte 0x1
 .uleb128 0x31
 .uleb128 0x13
 .uleb128 0x52
 .uleb128 0x1
 .uleb128 0x55
 .uleb128 0x6
 .uleb128 0x58
 .uleb128 0xb
 .uleb128 0x59
 .uleb128 0xb
 .uleb128 0x1
 .uleb128 0x13
 .byte 0x0
 .byte 0x0
 .uleb128 0x21
 .uleb128 0x5
 .byte 0x0
 .uleb128 0x31
 .uleb128 0x13
 .uleb128 0x1c
 .uleb128 0x5
 .byte 0x0
 .byte 0x0
 .uleb128 0x22
 .uleb128 0xb
 .byte 0x1
 .uleb128 0x55
 .uleb128 0x6
 .byte 0x0
 .byte 0x0
 .uleb128 0x23
 .uleb128 0x34
 .byte 0x0
 .uleb128 0x31
 .uleb128 0x13
 .uleb128 0x2
 .uleb128 0x6
 .byte 0x0
 .byte 0x0
 .uleb128 0x24
 .uleb128 0x5
 .byte 0x0
 .uleb128 0x31
 .uleb128 0x13
 .uleb128 0x2
 .uleb128 0x6
 .byte 0x0
 .byte 0x0
 .uleb128 0x25
 .uleb128 0x5
 .byte 0x0
 .uleb128 0x31
 .uleb128 0x13
 .byte 0x0
 .byte 0x0
 .uleb128 0x26
 .uleb128 0x1
 .byte 0x1
 .uleb128 0x49
 .uleb128 0x13
 .uleb128 0x1
 .uleb128 0x13
 .byte 0x0
 .byte 0x0
 .uleb128 0x27
 .uleb128 0x21
 .byte 0x0
 .uleb128 0x49
 .uleb128 0x13
 .uleb128 0x2f
 .uleb128 0xb
 .byte 0x0
 .byte 0x0
 .uleb128 0x28
 .uleb128 0x26
 .byte 0x0
 .uleb128 0x49
 .uleb128 0x13
 .byte 0x0
 .byte 0x0
 .uleb128 0x29
 .uleb128 0x5
 .byte 0x0
 .uleb128 0x31
 .uleb128 0x13
 .uleb128 0x1c
 .uleb128 0x7
 .byte 0x0
 .byte 0x0
 .uleb128 0x2a
 .uleb128 0xb
 .byte 0x1
 .uleb128 0x11
 .uleb128 0x1
 .uleb128 0x12
 .uleb128 0x1
 .uleb128 0x1
 .uleb128 0x13
 .byte 0x0
 .byte 0x0
 .uleb128 0x2b
 .uleb128 0x1d
 .byte 0x1
 .uleb128 0x31
 .uleb128 0x13
 .uleb128 0x11
 .uleb128 0x1
 .uleb128 0x12
 .uleb128 0x1
 .uleb128 0x58
 .uleb128 0xb
 .uleb128 0x59
 .uleb128 0x5
 .byte 0x0
 .byte 0x0
 .uleb128 0x2c
 .uleb128 0x1d
 .byte 0x1
 .uleb128 0x31
 .uleb128 0x13
 .uleb128 0x11
 .uleb128 0x1
 .uleb128 0x12
 .uleb128 0x1
 .uleb128 0x58
 .uleb128 0xb
 .uleb128 0x59
 .uleb128 0x5
 .uleb128 0x1
 .uleb128 0x13
 .byte 0x0
 .byte 0x0
 .uleb128 0x2d
 .uleb128 0x5
 .byte 0x0
 .uleb128 0x31
 .uleb128 0x13
 .uleb128 0x2
 .uleb128 0xa
 .byte 0x0
 .byte 0x0
 .uleb128 0x2e
 .uleb128 0xf
 .byte 0x0
 .uleb128 0xb
 .uleb128 0xb
 .uleb128 0x49
 .uleb128 0x13
 .byte 0x0
 .byte 0x0
 .uleb128 0x2f
 .uleb128 0x35
 .byte 0x0
 .uleb128 0x49
 .uleb128 0x13
 .byte 0x0
 .byte 0x0
 .byte 0x0
 .section .debug_pubnames,"",@progbits
 .long 0x64
 .value 0x2
 .long .Ldebug_info0
 .long 0xdec
 .long 0x3ad
 .string "setup_i8254"
 .long 0x462
 .string "setup_i8259"
 .long 0x5b7
 .string "i8259_configure_irq_trigger"
 .long 0x6c0
 .string "cache_as_ram_main"
 .long 0x0
 .section .debug_pubtypes,"",@progbits
 .long 0x87
 .value 0x2
 .long .Ldebug_info0
 .long 0xdec
 .long 0x25
 .string "uint8_t"
 .long 0x3e
 .string "uint16_t"
 .long 0x57
 .string "uint32_t"
 .long 0x7e
 .string "u8"
 .long 0x88
 .string "u16"
 .long 0x93
 .string "u32"
 .long 0xac
 .string "device_t"
 .long 0xb7
 .string "msr_struct"
 .long 0xde
 .string "msr_t"
 .long 0xe9
 .string "UINT32"
 .long 0xf4
 .string "UINT64"
 .long 0x0
 .section .debug_aranges,"",@progbits
 .long 0x1c
 .value 0x2
 .long .Ldebug_info0
 .byte 0x4
 .byte 0x0
 .value 0x0
 .value 0x0
 .long .Ltext0
 .long .Letext0-.Ltext0
 .long 0x0
 .long 0x0
 .section .debug_ranges,"",@progbits
.Ldebug_ranges0:
 .long .LBB244-.Ltext0
 .long .LBE244-.Ltext0
 .long .LBB247-.Ltext0
 .long .LBE247-.Ltext0
 .long 0x0
 .long 0x0
 .long .LBB245-.Ltext0
 .long .LBE245-.Ltext0
 .long .LBB246-.Ltext0
 .long .LBE246-.Ltext0
 .long 0x0
 .long 0x0
 .long .LBB254-.Ltext0
 .long .LBE254-.Ltext0
 .long .LBB257-.Ltext0
 .long .LBE257-.Ltext0
 .long 0x0
 .long 0x0
 .section .debug_str,"MS",@progbits,1
.LASF28:
 .string "pnp_exit_conf_state"
.LASF29:
 .string "result"
.LASF58:
 .string "boot_cpu"
.LASF24:
 .string "enable"
.LASF1:
 .string "signed char"
.LASF39:
 .string "bist"
.LASF5:
 .string "short int"
.LASF46:
 .string "int_bits"
.LASF14:
 .string "UINT32"
.LASF45:
 .string "is_level_triggered"
.LASF31:
 .string "__writemsr"
.LASF26:
 .string "index"
.LASF17:
 .string "pnp_write_config"
.LASF18:
 .string "outb"
.LASF20:
 .string "pnp_enter_conf_state"
.LASF27:
 .string "iobase"
.LASF22:
 .string "device"
.LASF55:
 .string "src/mainboard/amd/persimmon/romstage.c"
.LASF9:
 .string "long long int"
.LASF10:
 .string "long int"
.LASF35:
 .string "Data"
.LASF23:
 .string "pnp_set_enable"
.LASF50:
 .string "cpu_init_detectedx"
.LASF52:
 .string "spiBase"
.LASF34:
 .string "Port"
.LASF0:
 .string "unsigned char"
.LASF32:
 .string "Value"
.LASF47:
 .string "__func__"
.LASF25:
 .string "pnp_set_iobase"
.LASF41:
 .string "setup_i8254"
.LASF42:
 .string "setup_i8259"
.LASF33:
 .string "__outdword"
.LASF8:
 .string "long long unsigned int"
.LASF6:
 .string "uint32_t"
.LASF7:
 .string "unsigned int"
.LASF3:
 .string "uint16_t"
.LASF11:
 .string "long unsigned int"
.LASF4:
 .string "short unsigned int"
.LASF49:
 .string "cache_as_ram_main"
.LASF48:
 .string "char"
.LASF57:
 .string "msr_struct"
.LASF53:
 .string "save"
.LASF37:
 .string "f81865f_enable_serial"
.LASF13:
 .string "msr_t"
.LASF19:
 .string "port"
.LASF51:
 .string "reg8"
.LASF56:
 .string "e:\\temp\\persimmon_05-31-2011\\coreboot"
.LASF36:
 .string "__indword"
.LASF40:
 .string "cpuid_eax"
.LASF38:
 .string "report_bist_failure"
.LASF43:
 .string "i8259_configure_irq_trigger"
.LASF2:
 .string "uint8_t"
.LASF12:
 .string "device_t"
.LASF21:
 .string "pnp_set_logical_device"
.LASF16:
 .string "value"
.LASF15:
 .string "UINT64"
.LASF44:
 .string "int_num"
.LASF54:
 .string "GNU C 4.5.2"
.LASF30:
 .string "rdmsr"
 .ident "GCC: (coreboot toolchain v1.03 December 16th, 2010) 4.5.2"
# 6 "build/romstage/crt0.S" 2
